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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 92271-92280 / 2348439 (共234844頁)
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每頁顯示[10|25|50]項目
| 國立臺灣大學 |
2004-08 |
A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter
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Chen, Yu-Hsun; Lee, Tai-Cheng |
| 國立臺灣大學 |
2007 |
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers
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Shen, Ding-Lan; Lee, Tai-Cheng |
| 國立成功大學 |
2012-11 |
A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications
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Chen, Ren-Li; Chang, Soon-Jyh |
| 臺大學術典藏 |
2018-09-10T07:09:32Z |
A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification
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Feng-Chiu Hsieh;Tai-Cheng; Feng-Chiu Hsieh; Tai-Cheng; TAI-CHENG LEE |
| 國立中山大學 |
2005-08 |
A 6-bit SAR pipelined ADC using improved TIQ technology
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Yan-Huei Lee;Jyi-Tsong Lin |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 6-Gb/s Adaptive-Loop-Bandwidth Clock and Data Recovery (CDR) Circuits
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L-H Chiueh;T-C Lee; L-H Chiueh; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T09:25:30Z |
A 6-GHz All Digital PLL for Spread Spectrum Clock Generators (SSCG)
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C-D Su;C-W Lee;T-C Lee; C-D Su; C-W Lee; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2020-06-11T06:31:38Z |
A 6-GHz integer frequency synthesizer for SATA III applications in 0.18-μm CMOS technology
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Cheng, J.-H.;Lin, J.-A.;Wu, M.-H.;Tsai, J.-H.;Huang, T.-W.; Cheng, J.-H.; Lin, J.-A.; Wu, M.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator
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C-H Wong;T-C Lee; C-H Wong; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2020-06-11T06:31:34Z |
A 6-GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA-III applications
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Alsuraisry, H.;Cheng, J.-H.;Lin, J.-A.;Kuo, Y.-H.;Tsai, J.-H.;Huang, T.-W.; Alsuraisry, H.; Cheng, J.-H.; Lin, J.-A.; Kuo, Y.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG |
顯示項目 92271-92280 / 2348439 (共234844頁)
<< < 9223 9224 9225 9226 9227 9228 9229 9230 9231 9232 > >>
每頁顯示[10|25|50]項目
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