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Institution	Date	Title	Author
臺大學術典藏	2004-08	Hardware architecture design for visual processing: present and future	Tseng, Po-Chih; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2006-01	Hardware architecture design of an H.264/AVC video codec	Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee; Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee
國立臺灣大學	2006-01	Hardware architecture design of an H.264/AVC video codec	Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee
臺大學術典藏	2018-09-10T05:50:30Z	Hardware architecture design of an H.264/AVC video codec	Chen, T.-C.; Lian Jr.; C.; Chen, L.-G.; LIANG-GEE CHEN
國立臺灣大學	2011	Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation	Hsu, Kung-Yen; Chien, Shao-Yi
臺大學術典藏	2018-09-10T08:42:33Z	Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation	Hsu, Kung-Yen;Chien, Shao-Yi; Hsu, Kung-Yen; Chien, Shao-Yi; SHAO-YI CHIEN
臺大學術典藏	2018-09-10T09:22:24Z	Hardware architecture design of hybrid distributed video coding with frame level coding mode selection	Chiu, C.-C.; Wu, H.-F.; Chien, S.-Y.; Lee, C.-H.; Somayazulu, V.S.; Chen, Y.-K.; SHAO-YI CHIEN
國立臺灣大學	2005-08	Hardware architecture design of video compression for multimedia communication systems	Chien, Shao-Yi; Huang, Yu-Wen; Chen, Ching-Yeh; Chen, Homer H.; Chen, Liang-Gee
臺大學術典藏	2018-09-10T05:15:48Z	Hardware architecture design of video compression for multimedia communication systems	Chen, Liang-Gee; Chen, Homer H.; Chen, Ching-Yeh; Huang, Yu-Wen; LIANG-GEE CHEN; Chien, Shao-Yi; Chien, Shao-Yi; LIANG-GEE CHEN
臺大學術典藏	2018-09-10T04:47:19Z	Hardware architecture for global motion estimation for MPEG-4 advanced simple profile	Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN

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