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Institution	Date	Title	Author
國立臺灣科技大學	2009-04	Hardware Simplification to the Delta Path in a MASH 111 Delta–Sigma Modulator	Chia-Yu Yao;Chih-Chun Hsieh
國立臺灣大學	2009	HARDWARE SOFTWARE CO-DESIGN OF A MULTIMEDIA SOC PLATFORM	Chen, Sao-Jie; Lin, Guang-Huei; Hsiung, Pao-Ann; Hu, Yu–Hen
臺大學術典藏	2018-09-10T07:36:33Z	Hardware software co-design of a multimedia SOC platform	Hu, Yu-Hen;Hsiung, Pao-Ann;Lin, Guang-Huei;Chen, Sao-Jie; Hu, Yu-Hen; Hsiung, Pao-Ann; Lin, Guang-Huei; Chen, Sao-Jie; Chen, Sao-Jie
臺大學術典藏	1993-10	Hardware verification using symbolic state transition graphs	Chen, Pin-Hong; Shyu, Jyuo-Min; Chen, Liang-Gee; Chen, Pin-hong; Shyu, Jyuo-Min; Chen, Liang-Gee
國立臺灣大學	1993-10	Hardware verification using symbolic state transition graphs	Chen, Pin-hong; Shyu, Jyuo-Min; Chen, Liang-Gee
臺大學術典藏	2018-09-10T04:27:49Z	Hardware verification using symbolic state transition graphs	Chen, Pinhong; Shyu, Jyuo-Min; Chen, Liang-Gee; LIANG-GEE CHEN
臺大學術典藏	2020-06-11T06:29:41Z	Hardware Verification Using Symbolic State Transition Graphs.	Chen, Pinhong;Shyu, Jyuo-Min;Chen, Liang-Gee; Chen, Pinhong; Shyu, Jyuo-Min; Chen, Liang-Gee; LIANG-GEE CHEN
臺大學術典藏	2021-09-21T23:19:35Z	Hardware- And Memory-Efficient Architecture for Disparity Estimation of Large Label Counts	Wu, Sih Sian; Chen, Hon Hui; LIANG-GEE CHEN
臺大學術典藏	2020-05-04T08:04:29Z	Hardware-accelerated cache simulation for multicore by FPGA	Hung, S.-H.; Ho, Y.-M.; Yeh, C.-W.; Cheng-Yueh, Lee, C.-P.; SHIH-HAO HUNG
臺大學術典藏	2018	Hardware-accelerated cache simulation for multicore by FPGA.	SHIH-HAO HUNG; Lee, Chen-Pang; Liu, Cheng-Yueh; Yeh, Chih Wei; Ho, Yi-Mo; Hung, Shih-Hao

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