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Institution	Date	Title	Author
臺大學術典藏	2020-09-30T01:17:18Z	Low-power microcontroller solution for measuring HBR using single reflection SpO2 Sensor	Sun C.-C.; Chun K.-W.; Thai T.T.; YA-WEN YANG
臺大學術典藏	2018-09-10T09:42:58Z	Low-power multi-processor system architecture design for universal biomedical signal processing	Cheng, L.-F.;Chen, T.-C.;Chen, L.-G.; Cheng, L.-F.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN
國立高雄師範大學	2015-04-02	Low-Power Multi-Standard Viterbi Decoder for Wireless Communication Applications	鄭伯壎; C. Yu;B. S. Lin;Po-Hsun Cheng;Y. S. Su
中華大學	2009	Low-Power Multiplier Design with Row and Column Bypassing	顏金泰; YAN, JIN-TAI
中華大學	2006	Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters	宋志雲; Sung, Tze-Yun
中華大學	2006	Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters	謝曜式; Shieh, Yaw-Shih
國立交通大學	2014-12-08T15:35:28Z	Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors	Wang, Dao-Ping; Lin, Hon-Jarn; Chuang, Ching-Te; Hwang, Wei
國立臺灣大學	1998	Low-Power Multirate Architecture for IF Digital Frequency Down-Converter	Shyh-Jye Jou; Shou-Yang Wu; 汪重光; Shyh-Jye Jou; Shou-Yang Wu; Wang, Chorng-Kuang
國立臺灣大學	2004-05	Low-power parallel tree architecture for full search block-matching motion estimation	Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2018-09-10T04:47:18Z	Low-power parallel tree architecture for full search block-matching motion estimation	Lin, S.-S.; Tseng, P.-C.; Chen, L.-G.; Lin, S.-S.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN

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