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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:36:00Z	A 1-GS/s 6-Bit two-channel two-step ADC in 0.13-μm CMOS	Chen, H.-W.;Chen, I.-C.;Tseng, H.-C.;Chen, H.-S.; Chen, H.-W.; Chen, I.-C.; Tseng, H.-C.; Chen, H.-S.; HSIN-SHU CHEN
國立成功大學	2012-11	A 1-mu W 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications	Huang, Guan-Ying; Chang, Soon-Jyh; Liu, Chun-Cheng; Lin, Ying-Zu
淡江大學	2004-11	A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps	郭建宏; Kuo, Chien-hung; Liu, Shen-iuan
國立臺灣大學	2004	A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps	Kuo, Chien-Hung; Liu, Shen-Iuan
國立臺灣師範大學	2014-10-30T09:28:40Z	A 1-V 10.7MHz Fourth-Order Bandpass ΔΣ Modulators Using Two Switched Opamps	Chien-Hung Kuo; Shen-Iuan Liu
國立交通大學	2014-12-08T15:35:45Z	A 1-V 100-dB Dynamic Range 24.4-kHz Bandwidth Delta-Sigma Modulator	Chang, Chia-Ling; Wu, Jieh-Tsorng
臺大學術典藏	2018-09-10T03:50:14Z	A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell	P. F. Lin; J. B. Kuo; P. F. Lin; J. B. Kuo; JAMES-B KUO
國立臺灣大學	2001	A 1-V 128-kb four-way set-associative CMOS cache memory usingwordline-oriented tag-compare (WLOTC) structure with thecontent-addressable-memory (CAM) 10-transistor tag cell	Lin, Perng-Fei; Kuo, J.B.
國立交通大學	2019-10-05T00:08:42Z	A 1-V 175-mu W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques	Liao, Sheng-Hui; Wu, Jieh-Tsorng
國立交通大學	2014-12-08T15:25:52Z	A 1-V 2.4-GHz cmos frequency synthesizer with current-match charge pump	Wu, CY; Hsieh, CY; Chen, WM

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