| 南台科技大學 |
2001-05 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder
|
Chua-Chin Wang; Po-Ming Lee; Rong-Chin Lee; Chenn-Jung Huang; 王朝欽;李博明 |
| 南台科技大學 |
2001-05 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder
|
Chua-ChinWang; Po-Ming Lee; Rong-Chin Lee |
| 國立中山大學 |
2001-05 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder
|
C.C. Wang;P.M. Lee;R.C. Lee;C.T. Huang |
| 南台科技大學 |
2003-09 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
Chua-Chin Wang; Yih-Long Tseng; 李博明; Po-Ming Lee; Rong-Chin Lee; Chenn-Jung Hunng; 王朝欽 |
| 南台科技大學 |
2003-09 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
Chua-Chin Wang; Yih-Long Tseng; Po-Ming Lee; Rong-Chin Lee; Chenn-Jung Huang |
| 國立中山大學 |
2003 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
C.C. Wang;Y.L. Tseng;P.M. Lee;R.C. Lee;C.J. Huang |
| 國立中山大學 |
2003-09 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
C.C. Wang; Y.L. Tseng; P.M. Lee; R.C. Lee; C.J. Huang |
| 南台科技大學 |
2000-12 |
A 1.25 GHz 8-bit Tree-Structured Carry Lookahead Adder
|
Chua-Chin Wang; Po-Ming Lee; Chenn-Jung Huang; Rong-Chin Lee |
| 國立中山大學 |
2000-12 |
A 1.25 GHz 8-bit tree-structured carry lookahead adder
|
C.C. Wang;P.M. Lee;C.J. Huang;R.C. Lee |
| 國立臺灣科技大學 |
2008 |
A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition
|
Oulee C.-S.; Yang R.-J. |
| 臺大學術典藏 |
2018-09-10T08:18:16Z |
A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression
|
Chao-Ching Hung;I-Fong Chen;Shen-Iuan Liu; Chao-Ching Hung; I-Fong Chen; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立中山大學 |
2003-08 |
A 1.26ns access time current-mode sense amplifier design for SRAMs
|
C.C. Wang;Y.L. Tseng;C.C. Li;R. Hu |
| 元智大學 |
2015-08-04 |
A 1.2V 3.5Gbps Digitalized LVDS driver in 0.18um CMOS technology
|
Jhih-Siang Shao; Shi-Fung Zhou; Hungwen Lin |
| 淡江大學 |
1997-08 |
A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process
|
Cheng, Kuo-Hsing; Yee, Liow Yu; Liaw, Yii-Yih; Yang, Wei-Bin |
| 淡江大學 |
1997-08-21 |
A 1.2V 32-bit CMOS adder design using convertional 5V CMOS process
|
鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Laiw, Yii-yih |
| 臺大學術典藏 |
2020-06-11T06:45:52Z |
A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique
|
Wang, Y.-S.;Hsieh, M.-H.;Liu, C.-M.;Wu, Y.-C.;Lin, B.-F.;Chiu, H.-C.;Chen, C.C.-P.; Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Wu, Y.-C.; Lin, B.-F.; Chiu, H.-C.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 國立臺灣大學 |
2005-02 |
A 1.2V 6.7mW impulse-radio UWB baseband transceiver
|
Yang, Chia-Hsiang; Chen, Kuan-Hung; Chiueh, Tzi-Dar |
| 臺大學術典藏 |
2018-09-10T05:23:20Z |
A 1.2V 6.7mW impulse-radio UWB baseband transceiver
|
Yang, C.-H.; Chen, K.-H.; Chiueh, T.-D.; CHIA-HSIANG YANG |
| 國立交通大學 |
2014-12-08T15:03:56Z |
A 1.2V Interference-Sturdiness, DC-Offset Calibrated CMOS Receiver Utilizing a Current-Mode Filter for UWB
|
Shih, Horng-Yuan; Chen, Wei-Hsien; Juang, Kai-Chenug; Yang, Tzu-Yi; Kuo, Chien-Nan |
| 國立高雄師範大學 |
2008 |
A 1.2V Low-Power CMOS Voltage-Controlled Oscillator (VCO) Using Current-Reused Configuration with Balanced Resistors for IEEE 802.16e
|
Ruey-Lue Wang;Hsuan-Der Yen;Wen-Kuan Yeh;Yi-Jiue Shie; 王瑞祿 |
| 淡江大學 |
1997-08 |
A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic
|
Cheng, Kuo-Hsing; Chen, Jian-Hung |
| 國立臺灣大學 |
2004-08 |
A 1.2V, 18mW, 10Gb/s SiGe transimpedance amplifier
|
Lee, Chihun; Wu, Chia-Hsin; Liu, Shen-Iuan |
| 國立交通大學 |
2017-04-21T06:48:28Z |
A 1.3 GHz-5.3 GHz Wideband, High Linearity Balun Low Noise Amplifier
|
Yang, Kai-Hsiang; Kuo, Ming-Ching; Yan, Tzu-Chao; Kuo, Chien-Nan |
| 國立成功大學 |
2015-06 |
A 1.3 mW Low-IF, Current-Reuse, and Current-Bleeding RF Front-End for the MICS Band With Sensitivity of-97 dBm
|
Cruz, Hugo; Huang, Hong-Yi; Lee, Shuenn-Yuh; Luo, Ching-Hsing |
| 國立交通大學 |
2017-04-21T06:56:16Z |
A 1.3-2.08 GHz Filtering Power Divider With Bandwidth Control and High In-Band Isolation
|
Chi, Pei-Ling; Yang, Tao |
