| 國立交通大學 |
2017-04-21T06:49:32Z |
A 14-bit Oversampled Delta-Sigma Modulator for Silicon Condenser Microphones
|
Chiang, Cheng-Ta; Huang, Yu-Chung |
| 淡江大學 |
2003-08 |
A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming
|
Cheng, Kuo-Hsing; Li, Po-Yu; Chen, Tsung-Shen |
| 國立交通大學 |
2018-08-21T05:53:03Z |
A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path
|
Hsieh, E. Ray; Kuo, Yen Chen; Cheng, Chih-Hung; Kuo, Jing Ling; Jiang, Meng-Ru; Lin, Jian-Li; Chen, Hung-Wen; Chung, Steve S.; Liu, Chuan-Hsi; Chen, Tse Pu; Huang, Shih An; Chen, Tai-Ju; Cheng, Osbert |
| 中國醫藥大學 |
2013-12-07 |
A 14-years-old boy presented with bile stained vomitus
|
林佐臨(Tso-Lin Lin);吳淑芬(Shu-Fen Wu);陳安琪(An-Chyi Chen);陳偉德(Walter Chen);彭慶添(Ching-Tien Peng) |
| 國立中山大學 |
2006-12 |
A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing
|
C.C. Wang;C.C. Huang;J.S. Liou;K.W. Fang |
| 臺大學術典藏 |
2020-06-04T07:53:32Z |
A 140-GHz Monolithic Low Noise Amplifier
|
Wang, H.;Lai, R.;Lo, D.C.W.;Streit, D.C.;Liu, P.H.;Dia, R.M.;Berenz, J.; Wang, H.; Lai, R.; Lo, D.C.W.; Streit, D.C.; Liu, P.H.; Dia, R.M.; Berenz, J.; HUEI WANG |
| 臺大學術典藏 |
2018-09-10T07:42:00Z |
A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage
|
Hwei-Yu Lee;Shen-Iuan Liu; Hwei-Yu Lee; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立交通大學 |
2018-08-21T05:57:01Z |
A 145 mu W 315MHz Harmonically Injection-Locked RF Transmitter with Two-Step Frequency Multiplication Techniques
|
Dau, Nan; Chen, Yen-Ting; Liao, Yu-Te |
| 國立交通大學 |
2014-12-08T15:34:49Z |
A 147 GHz Fully Differential D-Band Amplifier Design in 65 nm CMOS
|
Li, Chun-Hsing; Lai, Chih-Wei; Kuo, Chien-Nan |
| 臺大學術典藏 |
2013 |
A 147 GHz fully differential D-band amplifier design in 65 nm CMOS
|
CHUN-HSING LI; CHUN-HSING LI; and Chien-Nan Kuo; Chih-Wei Lai; Chun-Hsing Li; Chun-Hsing Li;Chih-Wei Lai;and Chien-Nan Kuo;CHUN-HSING LI |
| 臺大學術典藏 |
2018-09-10T03:29:20Z |
A 14b 20MSample/s CMOS pipelined ADC
|
Chen, H.-S.; Bacrania, K.; Song, B.-S.; HSIN-SHU CHEN |
| 國立臺灣大學 |
2001 |
A 14b 20MSamples/s CMOS Pipelined ADC
|
Chen, Hsin-Shu; Song, Bang-Sup; Bacrania, Kantilal |
| 臺大學術典藏 |
2018-09-10T07:08:37Z |
A 15-20GHz delay-locked loop in 90nm CMOS technology
|
Jung-Yu Chang;Chi-Nan Chuang;Shen-Iuan Liu; Jung-Yu Chang; Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-04T07:54:06Z |
A 15-50 GHz broadband resistive FET ring mixer using 0.18-μm CMOS technology
|
Chen, J.-H.;Kuo, C.-C.;Hsin, Y.-M.;Wang, H.; Chen, J.-H.; Kuo, C.-C.; Hsin, Y.-M.; Wang, H.; HUEI WANG |
| 臺大學術典藏 |
2018-09-10T04:14:59Z |
A 15-80GHz MMIC SPDT switch using traveling wave concept
|
W. H. Tu; P. Y. Chen; K. Y. Lin; H. Wang; R. B. Wu; S. S. Lu; RUEY-BEEI WU |
| 國立交通大學 |
2014-12-08T15:19:12Z |
A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration
|
Liu, HC; Lee, ZM; Wu, JT |
| 國立成功大學 |
2019 |
A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique
|
Wang, J.-C.;Hung, T.-C.;Kuo, T.-H. |
| 國立交通大學 |
2014-12-08T15:18:11Z |
A 15-bit 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration (vol 40, pg 1047, 2005)
|
Liu, HC; Lee, ZM; Wu, JT |
| 國立臺灣大學 |
2006 |
A 15-Gb/s 2:1 multiplexer in 0.18-μm CMOS
|
Chien, Jun-Chau; Lu, Liang-Hung |
| 臺大學術典藏 |
2021-03-12T08:41:05Z |
A 15-Gb/s 2:1 multiplexer in 0.18-μm CMOS
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
| 臺大學術典藏 |
2018-09-10T08:47:26Z |
A 15-mW 2.4-GHz IEEE 802.15.4 Transmitter with a FIR-embedded Phase Modulator
|
Y.-H. Liu; H.-H. Lo; T.-H. Lin; TSUNG-HSIEN LIN |
| 國立成功大學 |
2015 |
A 15-Year Nationwide Epidemiological Analysis of Guillain-Barre Syndrome in Taiwan
|
Huang, Wan-Chun; Lu, Chin-Li; Chen, Solomon Chih-Cheng |
| 國立臺灣大學 |
2007 |
A 15/30-GHz Dual-Band Multiphase Voltage-Controlled Oscillator in 0.18- μm CMOS
|
Hsieh, Hsieh-Hung; Hsu, Ying-Chih; Lu, Liang-Hung |
| 國立臺灣大學 |
1999 |
A 155-MHz BiCMOS automatic gain control amplifier
|
Huang, Po-Chiun; Huang, Chen-Yi; Wang, Chorng-Kuang |
| 國立臺灣大學 |
2006 |
A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit
|
Yang, Rong-Jyi; Chao, Kuan-Hua; Hwu, Sy-Chyuan; Liang, Chuan-Kang; Liu, Shen-Iuan |
