| 元智大學 |
2009-06 |
A 1.7-mW, 14.4% Frequency Tuning, 24GHz VCO with Current-Reused Structure Using 0.18-um CMOS Technology
|
蔡政翰; Yen-Hung Kuo; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:46Z |
A 1.7-mW, 14.4% Frequency Tuning,24GHz VCO with Current-Reused Structure Using 0.18-μm CMOS Technology
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang |
| 臺大學術典藏 |
2018-09-10T07:42:57Z |
A 1.7-mW, 16.8% Frequency Tuning, 24-GHz Transformer-Based LC-VCO using 0.18-um CMOS Technology
|
Yen-Hung Kuo;Jeng-Han Tsai;Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; TIAN-WEI HUANG |
| 國立交通大學 |
2014-12-08T15:26:52Z |
A 1.75GHz inductor-less CMOS low noise amplifier with high-Q active inductor load
|
Yang, JN; Cheng, YC; Hsu, TY; Hsu, TR; Lee, CY |
| 國立交通大學 |
2014-12-08T15:24:51Z |
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
|
Chao, Tzu-Chiang; Hwang, Wei |
| 國立臺灣大學 |
2004-08 |
A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 元智大學 |
2014-04-26 |
A 1.8 GHz CMOS High-Linear Power-Combining Power Amplifier Using On-Chip Transmission Line Transformer
|
Ming-Yi Chen; Jeng-Rern Yang |
| 國立中山大學 |
2009-12 |
A 1.8 V to 3.3 V Level-Converting Flip-Flop Design for Multiple Power Supply Systems
|
C.C. Wang;K.S.M. Li;S.J. Wang |
| 國立交通大學 |
2014-12-08T15:25:41Z |
A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end
|
Chen, WZ; Cheng, YL; Lin, DS |
| 臺大學術典藏 |
2021-03-12T08:40:55Z |
A 1.8-GHz Near-Field Dielectric Plethysmography Heart-Rate Sensor with Time-Based Edge Sampling
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
| 國立交通大學 |
2014-12-08T15:18:59Z |
A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end
|
Chen, WZ; Cheng, YL; Lin, DS |
| 淡江大學 |
2013-06 |
A 1.8-V 4-ppm oC Reference Current with Process and Temperature
|
Yang, Wei-Bin; Hong, Ming-Hao; Yeh, Sheng-Shuh |
| 淡江大學 |
2015/09/13 |
A 1.8-V Temperature Coefficient is 4.36-ppm/°C Bandgap Reference Current with Process Calibration
|
Yang, Wei-Bin |
| 元智大學 |
2016-06-23 |
A 1.8/2.6 GHz CMOS High Linearity Power Amplifier for LTE application
|
Chih-Huang Lin; Jeng-Rern Yang |
| 國立交通大學 |
2019-04-02T06:04:51Z |
A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS
|
Ku, Fang-Ju; Wu, Tung-Yu; Liao, Yen-Chin; Chang, Hsie-Chia; Wong, Wing Hung; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:27:18Z |
A 1.8GHz CMOS quadrature voltage-controlled oscillator (VCO) using the constant-current LC ring oscillator structure
|
Wu, CY; Kao, HS |
| 國立臺灣大學 |
2004-08 |
A 1.8V 2.5-5.2 GHz CMOS dual-input two-stage ring VCO
|
Tu, Wei-Hsuan; Yeh, Jyh-Yih; Tsai, Hung-Chieh; Wang, Chorng-Kuang |
| 國立高雄師範大學 |
2007-09 |
A 1.8V cascoded differential CMOS LNA for WCDMA receiver front-end
|
Jian-Ming Wu;Y. S. Lin;D. Y. Tsao;S. C. Li; 吳建銘 |
| 臺大學術典藏 |
2020-01-17T07:44:50Z |
A 1.9 GHz CMOS high isolation absorptive OOK modulator
|
Ling, C.-C.; Yang, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; JAU-HORNG CHEN |
| 臺大學術典藏 |
2020-11-03T09:53:14Z |
A 1.9-mW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Huang S.-A.;Chang K.-C.;Horng-Huei Liou;Yang C.-H.; Huang S.-A.; Chang K.-C.; HORNG-HUEI LIOU; Yang C.-H. |
| 臺大學術典藏 |
2021-02-26T08:42:03Z |
A 1.9-mW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Huang, S.-A.; Chang, K.-C.; Liou, H.-H.; Yang, C.-H.; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2021-02-26T08:42:04Z |
A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems
|
Wen, C.-C.; Lee, Y.-C.; Wu, Y.-C.; Kao, C.-C.; Yang, C.-H.; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2018-09-10T15:26:09Z |
A 1.96 mm 2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols
|
CR Tsai;MC Hsiao;WC Shen;AYA Wu;CM Cheng; CR Tsai; MC Hsiao; WC Shen; AYA Wu; CM Cheng; CHEN-MOU CHENG; AN-YEU(ANDY) WU |
| 國立交通大學 |
2014-12-08T15:09:28Z |
A 1.9mW portable ADPLL-based frequency synthesizer for high speed clock generation
|
Chang, Ming-Hung; Yang, Zong-Xi; Hwang, Wei |
| 臺大學術典藏 |
2020-02-26T07:30:06Z |
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Huang S.-A; Chang K.-C; HORNG-HUEI LIOU; Yang C.-H. |
| 臺大學術典藏 |
2018 |
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Yang C.-H.; HORNG-HUEI LIOU; Chang K.-C.; Huang S.-A.; Huang S.-A.;Chang K.-C.;Horng-Huei Liou;Yang C.-H. |
| 中華大學 |
2005 |
A 10 Bit 40-MS/s Pipelined Analog-to-Digital Converter for IEEE 802.11a WLAN Systems
|
田慶誠; Tien, Ching-Cheng |
| 中華大學 |
2006 |
A 10 Bit 40-MS/s Pipelined Analog-to-Digital Converter for IEEE 802.16 WiMAX Systems
|
田慶誠; Tien, Ching-Cheng |
| 中華大學 |
2007 |
A 10 Bit 40-MS/s Pipelined Analog-to-Digital Converter for WLAN Systems
|
田慶誠; Tien, Ching-Cheng |
| 國立交通大學 |
2014-12-08T15:30:06Z |
A 10 Gb/s Adaptive Cable Equalizer Using Phase Detection Technique in 0.13 mu m CMOS Technology
|
Chen, Kuang-Ren; Tsai, Chia-Ming; You, Sheng-Kai; Li, An-Siou; Chen, Wen-Tsao |
| 臺大學術典藏 |
2004-05 |
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier
|
Tsai, Hung-Chieh; Yeh, Jyh-Yih; Tu, Wei-Hsuan; Lee, Tai-Cheng; Wang, Chorng-Kuang; Tsai, Hung-Chieh; Yeh, Jyh-Yih; Tu, Wei-Hsuan; Lee, Tai-Cheng; Wang, Chorng-Kuang |
| 國立臺灣大學 |
2004-05 |
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier
|
Tsai, Hung-Chieh; Yeh, Jyh-Yih; Tu, Wei-Hsuan; Lee, Tai-Cheng; Wang, Chorng-Kuang |
| 國立交通大學 |
2014-12-08T15:25:19Z |
A 10 GHz low power CMOS quadrature voltage-controlled oscillator
|
Tarng, Shih-Hao; Jou, Christina F. |
| 臺大學術典藏 |
2009 |
A 10 GHz Phase-Locked Loop With a Compact Low-Pass Filter in 0.18 um CMOS
|
Li, Sin-Jhih; Hsieh, Hsieh-Hung; Lu, Liang-Hung; Li, Sin-Jhih; Hsieh, Hsieh-Hung; Lu, Liang-Hung |
| 國立臺灣大學 |
2009 |
A 10 GHz Phase-Locked Loop With a Compact Low-Pass Filter in 0.18 um CMOS
|
Li, Sin-Jhih; Hsieh, Hsieh-Hung; Lu, Liang-Hung |
| 臺大學術典藏 |
2018-09-10T07:43:05Z |
A 10 GHz phase-locked loop with a compact low-pass filter in 0.18 μm CMOS
|
S.-J. Li;H.-H. Hsieh;L.-H. Lu; S.-J. Li; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU |
| 臺大學術典藏 |
2009 |
A 10 GHz phase-locked loop with a compact low-pass filter in 0.18 μm CMOS
|
Li, S.-J.;Hsieh, H.-H.;Lu, L.-H.; Li, S.-J.; Hsieh, H.-H.; Lu, L.-H.; LIANG-HUNG LU |
| 國立交通大學 |
2014-12-08T15:15:22Z |
A 10 similar to 18GHz wide-band transfonner feedback LNA
|
Chiang, Pei-Yuan; Jou, Christina. F.; Wu, Hui-I; Huang, Zhe-Yang |
| 中國醫藥大學 |
2012-12-08 |
A 10 year-old boy bilious vomiting and abdominal pain for 2 weeks
|
黃鈺婷(Yu-Ting Huang);陳安琪(An-Chyi Chen);吳淑芬(Shu-Fen Wu);陳偉德(Walter Chen);黃鈺婷(Yu-Ting Huang) |
| 國立交通大學 |
2014-12-08T15:14:09Z |
A 10-110 GHz fundamental/harmonic rat-race mixer
|
Chi, Chun-Hsiang; Wu, Chung-Hung; Wang, Wei-Ting; Lai, Chi-Hau; Niu, Dow-Chih; Chang, Chi-Yang |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 10-20 Gb/s CDR circuit with 6200ppm frequency tracking
|
Huang, C.-C.;Tseng, K.-W.;Liu, S.-I.; Huang, C.-C.; Tseng, K.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 國立臺灣大學 |
2008-07 |
A 10-35 GHz low power bulk-driven mixer using 0.13-μm CMOS process
|
Kuo, Chun-Lin; Huang, Bo-Jr; Kuo, Che-Chung; Lin, Kun-You; Wang, Huei |
| 國立成功大學 |
2009-02 |
A 10-40 GHZ, Broadband Subharmonic Monolithic Mixer in 0.18 mu m CMOS Technology
|
Lin, Chih-Ming; Lin, Hua-Kuei; Lai, Yu-Ann; Chang, Chieh-Pin; Wang, Yeong-Her |
| 國立交通大學 |
2014-12-08T15:03:43Z |
A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCES
|
CHIN, SY; WU, CY |
| 臺大學術典藏 |
2018-09-10T09:21:52Z |
A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC
|
Tseng, C.-J.;Chen, H.-W.;Shen, W.-T.;Cheng, W.-C.;Chen, H.-S.; Tseng, C.-J.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.; HSIN-SHU CHEN |
| 國立暨南國際大學 |
2013 |
A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs
|
蕭敬民; Hsiao, CM |
| 國立暨南國際大學 |
2013 |
A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs
|
尹邦嚴; Yin, PY |
| 國立成功大學 |
2019 |
A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC
|
Hu, Hu H.-J.;Cheng, Y.-S.;Chang, S.-J. |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques
|
Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE |
| 國立臺灣科技大學 |
2017 |
A 10-bit 100-MS/s 2b/cycle-Assisted SAR ADC in 180nm CMOS
|
Chung, Y.-H.;Tseng, H.-W. |
