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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 90976-90985 / 2351361 (共235137頁)
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每頁顯示[10|25|50]項目
| 元智大學 |
2009-06 |
A 1.7-mW, 14.4% Frequency Tuning, 24GHz VCO with Current-Reused Structure Using 0.18-um CMOS Technology
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蔡政翰; Yen-Hung Kuo; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:46Z |
A 1.7-mW, 14.4% Frequency Tuning,24GHz VCO with Current-Reused Structure Using 0.18-μm CMOS Technology
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang |
| 臺大學術典藏 |
2018-09-10T07:42:57Z |
A 1.7-mW, 16.8% Frequency Tuning, 24-GHz Transformer-Based LC-VCO using 0.18-um CMOS Technology
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Yen-Hung Kuo;Jeng-Han Tsai;Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; TIAN-WEI HUANG |
| 國立交通大學 |
2014-12-08T15:26:52Z |
A 1.75GHz inductor-less CMOS low noise amplifier with high-Q active inductor load
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Yang, JN; Cheng, YC; Hsu, TY; Hsu, TR; Lee, CY |
| 國立交通大學 |
2014-12-08T15:24:51Z |
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
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Chao, Tzu-Chiang; Hwang, Wei |
| 國立臺灣大學 |
2004-08 |
A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector
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Yang, Rong-Jyi; Liu, Shen-Iuan |
| 元智大學 |
2014-04-26 |
A 1.8 GHz CMOS High-Linear Power-Combining Power Amplifier Using On-Chip Transmission Line Transformer
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Ming-Yi Chen; Jeng-Rern Yang |
| 國立中山大學 |
2009-12 |
A 1.8 V to 3.3 V Level-Converting Flip-Flop Design for Multiple Power Supply Systems
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C.C. Wang;K.S.M. Li;S.J. Wang |
| 國立交通大學 |
2014-12-08T15:25:41Z |
A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end
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Chen, WZ; Cheng, YL; Lin, DS |
| 臺大學術典藏 |
2021-03-12T08:40:55Z |
A 1.8-GHz Near-Field Dielectric Plethysmography Heart-Rate Sensor with Time-Based Edge Sampling
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JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
顯示項目 90976-90985 / 2351361 (共235137頁)
<< < 9093 9094 9095 9096 9097 9098 9099 9100 9101 9102 > >>
每頁顯示[10|25|50]項目
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