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Institution	Date	Title	Author
國立臺灣大學	2005	A 4-GHz phase shifter MMIC in 0.18-μm CMOS	Lu, Liang-Hung; Liao, Yu-Te
國立彰化師範大學	2004	A 4-Inch QVGA AMCNT-FED Driven by High Voltage LTPS-TFTs	Tseng, H. Y. ; Wang, Yu-Wu; Chen, C. M. ; Huang, C. Y. ; Sheu, S. S. ; Lin, W. Y. ; Lee, C. T. ; Chen, T. H. ; Wu, P. S. ; Yeh, Y. H. ; Lee, C. C.
臺大學術典藏	2021-09-02T00:04:13Z	A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors	Chiu Y.-C;Zhang Z;Chen J.-J;Si X;Liu R;Tu Y.-N;Su J.-W;Huang W.-H;Wang J.-H;Wei W.-C;Hung J.-M;Sheu S.-S;Li S.-H;Wu C.-I;Liu R.-S;Hsieh C.-C;Tang K.-T;Chang M.-F.; Chiu Y.-C; CHIH-I WU et al.
國立中山大學	2004	A 4-Kb 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches	C.C. Wang;Y.L. Tseng;H.Y. Leo;R. Hu
國立中山大學	2004-09	A 4-Kb 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches	C.C. Wang;Y.L. Tseng;H.Y. Leo;R. Hu
國立中山大學	2002-08	A 4-Kb 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches	C.C. Wang;H.Y. Leo;R. Hu
國立中山大學	2003-02	A 4-Kb 667-MHz CMOS SRAM using dynamic threshold voltage wordline transistors	C.C. Wang;T.H. Chen;R. Hu
國立中山大學	2006-05	A 4-Kb Low Power 4-T SRAM Design with Negative Word-Line Gate Drive	C.C. Wang;C.L. Lee;W.J. Lin
國立中山大學	2007	A 4-Kb low power SRAM design with negative word-line scheme	C.C. Wang;C.L. Lee;W.J. Lin
國立中山大學	2007-05	A 4-Kb low power SRAM design with negative word-line scheme	C.C. Wang;C.L. Lee;W.J. Lin

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