|
English
|
正體中文
|
简体中文
|
Total items :2853524
|
|
Visitors :
45221188
Online Users :
999
Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Title
|
Showing items 91991-92000 of 2346275 (234628 Page(s) Totally) << < 9195 9196 9197 9198 9199 9200 9201 9202 9203 9204 > >> View [10|25|50] records per page
| 臺大學術典藏 |
2020-06-11T06:16:47Z |
A 40.4-dB Range, 0.73-dB Step, and 0.07-dB Error Programmable Gain Amplifier Using Gain Error Shifting Technique
|
Wang, L.-S.;Ku, P.-C.;Ko, P.-T.;Chung, C.-J.;Lu, L.-H.; Wang, L.-S.; Ku, P.-C.; Ko, P.-T.; Chung, C.-J.; Lu, L.-H.; LIANG-HUNG LU |
| 國立成功大學 |
2019 |
A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth
|
Hung, T.-C.;Kuo, T.-H. |
| 淡江大學 |
2010-12-12 |
A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process
|
施鴻源; 陳秋榜 |
| 淡江大學 |
2012-07-15 |
A 400 MHz 500-fs-Jitter Open-Loop DLL-Based Multi-Phase Clock Generator Utilizing an Noise-Free All-Digital Locking Detection Circuitry
|
Shih, Horng-Yuan; Chang, Yu-Chuan; Chen, Chun-Fan; Lin, Sheng-Kai |
| 臺大學術典藏 |
2018-09-10T08:19:11Z |
A 400-MHz Super-Regenerative Receiver with a Fast Digital Frequency Calibration
|
H.-H. Liu;C.-J. Tung;Y.-H. Liu;T.-H. Lin; H.-H. Liu; C.-J. Tung; Y.-H. Liu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-μm CMOS
|
K.-C. Liao;P.-S. Huang;W.-H. Chiu;T.-H. Lin; K.-C. Liao; P.-S. Huang; W.-H. Chiu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T09:42:58Z |
A 401GFlops/W 16-cores signal reconstruction platform with a 4G entries/s matrix generation engine for compressed sensing and sparse representation
|
Tsai, Y.-M.;Yang, T.-J.;Chen, L.-G.; Tsai, Y.-M.; Yang, T.-J.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立交通大學 |
2019-04-02T06:04:27Z |
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems
|
Ng, Chee-Kit; Lin, Yu-Chun; Liu, Wei-Chang; Wu, Chin-Feng; Lou, Shyh-Lye |
| 臺大學術典藏 |
2018-09-10T07:42:01Z |
A 40Gb/s decision feedback equalizer using back-gate feedback technique
|
Chang-Lin Hsieh;Shen-Iuan Liu; Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T07:06:07Z |
A 40Gb/s TX and RX chip set in 65nm CMOS
|
Chen, M.-S.;Shih, Y.-N.;Lin, C.-L.;Hung, H.-W.;Lee, J.; Chen, M.-S.; Shih, Y.-N.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE |
Showing items 91991-92000 of 2346275 (234628 Page(s) Totally) << < 9195 9196 9197 9198 9199 9200 9201 9202 9203 9204 > >> View [10|25|50] records per page
|