| 國立交通大學 |
2014-12-08T15:18:53Z |
A 5.7 GHz Gilbert upconversion mixer with an LC current combiner output using 0.35 mu m SiGe HBT technology
|
Wu, TH; Meng, CC; Huang, GW |
| 國立臺灣大學 |
2002 |
A 5.7 GHz interpolative VCO using InGaP/GaAs HBT technology
|
Yu, Shih-An; Meng, Chin-Chun; Lu, Shey-Shi |
| 國立成功大學 |
2003-12 |
A 5.7-GHz 0.18-mu m CMOS gain-controlled differential LNA with current reuse for WLAN receiver
|
Chu, Yuan-Kai; Liao, Che-Hong; Chuang, Huey-Ru |
| 東海大學 |
2009 |
A 5.7-GHz low-noise amplifier with source-degenerated active inductor
|
Chu, C.-H., Huang, I.-L., Lin, Y.-H., Gong, J. |
| 國立臺灣大學 |
2009 |
A 5.79 dB NF, 30-GHz-Band Monolithic LNA with 10 mW Power Consumption in Standard 0.18 μm CMOS Technology
|
Chen, Chi-Chen; Lin, Yo-Sheng; Huang, Guo-Wei; Lu, Shey-Shi |
| 國立暨南國際大學 |
2009 |
A 5.79-dB NF, 30-GHz-BAND MONOLITHIC LNA WITH 10 mW POWER CONSUMPTION IN STANDARD 0.18-mu m CMOS TECHNOLOGY?
|
陳志成?; Chen, CC |
| 國立暨南國際大學 |
2009 |
A 5.79-dB NF, 30-GHz-BAND MONOLITHIC LNA WITH 10 mW POWER CONSUMPTION IN STANDARD 0.18-mu m CMOS TECHNOLOGY?
|
林佑昇?; Lin, YS |
| 國立交通大學 |
2014-12-08T15:24:02Z |
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications
|
Yen, Shao-Wei; Hung, Shiang-Yu; Chen, Chih-Lung; Chang, Hsie-Chia; Jou, Shyh-Jye; Lee, Chen-Yi |
| 元智大學 |
2004-09 |
A 5.8 GHz Low-Power, Low-Phase-Noise CMOS LC VCO for IEEE 802.11a Applications
|
吳紹懋; 林昀賢 |
| 國立交通大學 |
2016-03-28T00:04:19Z |
A 5.8 mW Continuous-Time Delta Sigma Modulator With 20 MHz Bandwidth Using Time-Domain Flash Quantizer
|
Chen, Zong-Yi; Hung, Chung-Chih |
| 國立臺灣科技大學 |
2016 |
A 5.8-GHz CMOS low-power active mixer featuring high conversion gain and low LO driving power
|
Chang, S.-H;Huang, J.-K;Tsneg, C.-H. |
| 元智大學 |
2003-09 |
A 5.8-GHz CMOS VCO with Injection-locked frequency divider for IEEE 802.11a application
|
吳紹懋; 陳威良 |
| 元智大學 |
2003-08 |
A 5.8-GHz Fractional-N Frequency Synthesizer for IEEE 802.11a Application
|
吳紹懋; 陳威良; 林昀賢 |
| 國立臺灣科技大學 |
2011 |
A 5.8-GHz FREQUENCY SYNTHESIZER CHIP DESIGN FOR WORLDWIDE INTEROPERABILITY FOR MICROWAVE ACCESS APPLICATION
|
Huang, J.F.;Shih, C.W.;Liu, R.Y. |
| 國立臺灣科技大學 |
2014 |
A 5.8-GHz frequency synthesizer with dynamic current-matching charge pump linearization technique and an average varactor circuit
|
Huang J.-F., Yang J.-L., Chen K.-L. |
| 臺大學術典藏 |
2018-09-10T07:35:50Z |
A 5.8-GHz GaAs based HBT amplifier with novel RF ESD protection
|
Huang, B.-J.;Lin, K.-Y.;Chiong, C.-C.;Wang, H.; Huang, B.-J.; Lin, K.-Y.; Chiong, C.-C.; Wang, H.; KUN-YOU LIN |
| 元智大學 |
2003-06 |
A 5.8-GHz high efficient, low power, low phase noise CMOS VCO for IEEE 802.11a
|
吳紹懋; Ron-Yi Liu; Wei-Liang Chen |
| 國立臺灣科技大學 |
2016 |
A 5.8-GHz radar sensor chip in 0.18-μm CMOS for non-contact vital sign detection
|
Huang, J.-K;Tseng, C.-H. |
| 臺大學術典藏 |
2002-06 |
A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology
|
Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang; Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang |
| 國立臺灣大學 |
2002-06 |
A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology
|
Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang |
| 元智大學 |
2002-08 |
A 5.8Ghz CMOS RF Image-Rejection Receiver Front-end using 90-degree Delayed-Lock Loop
|
吳紹懋; Ron-Yi Liu; Sin-Yu Chen |
| 元智大學 |
2003-10 |
A 5.8GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications
|
吳紹懋; 劉榮宜; 陳威良 |
| 臺大學術典藏 |
2018-09-10T08:14:45Z |
A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs
|
Yang, C.-H.;Yu, T.-H.;Markovi?, D.; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG |
| 國立交通大學 |
2019-09-02T07:45:41Z |
A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems
|
Ng, Chee-Kit; Lin, Yu-Chun; Jou, Shyh-Tye |
| 國立交通大學 |
2019-10-05T00:09:47Z |
A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems
|
Ng, Chee-Kit; Chiu, Kang-Lun; Lin, Yu-Chun; Jou, Shyh-Jye |
