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Institution Date Title Author
臺大學術典藏 2018-09-10T07:35:50Z A 5.8-GHz GaAs based HBT amplifier with novel RF ESD protection Huang, B.-J.;Lin, K.-Y.;Chiong, C.-C.;Wang, H.; Huang, B.-J.; Lin, K.-Y.; Chiong, C.-C.; Wang, H.; KUN-YOU LIN
元智大學 2003-06 A 5.8-GHz high efficient, low power, low phase noise CMOS VCO for IEEE 802.11a 吳紹懋; Ron-Yi Liu; Wei-Liang Chen
國立臺灣科技大學 2016 A 5.8-GHz radar sensor chip in 0.18-μm CMOS for non-contact vital sign detection Huang, J.-K;Tseng, C.-H.
臺大學術典藏 2002-06 A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang; Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang
國立臺灣大學 2002-06 A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang
元智大學 2002-08 A 5.8Ghz CMOS RF Image-Rejection Receiver Front-end using 90-degree Delayed-Lock Loop 吳紹懋; Ron-Yi Liu; Sin-Yu Chen
元智大學 2003-10 A 5.8GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications 吳紹懋; 劉榮宜; 陳威良
臺大學術典藏 2018-09-10T08:14:45Z A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs Yang, C.-H.;Yu, T.-H.;Markovi?, D.; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG
國立交通大學 2019-09-02T07:45:41Z A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems Ng, Chee-Kit; Lin, Yu-Chun; Jou, Shyh-Tye
國立交通大學 2019-10-05T00:09:47Z A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems Ng, Chee-Kit; Chiu, Kang-Lun; Lin, Yu-Chun; Jou, Shyh-Jye

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