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Institution	Date	Title	Author
元智大學	2002-08	A 5.8Ghz CMOS RF Image-Rejection Receiver Front-end using 90-degree Delayed-Lock Loop	吳紹懋; Ron-Yi Liu; Sin-Yu Chen
元智大學	2003-10	A 5.8GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications	吳紹懋; 劉榮宜; 陳威良
臺大學術典藏	2018-09-10T08:14:45Z	A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs	Yang, C.-H.;Yu, T.-H.;Markovi?, D.; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG
國立交通大學	2019-09-02T07:45:41Z	A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems	Ng, Chee-Kit; Lin, Yu-Chun; Jou, Shyh-Tye
國立交通大學	2019-10-05T00:09:47Z	A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems	Ng, Chee-Kit; Chiu, Kang-Lun; Lin, Yu-Chun; Jou, Shyh-Jye
國立臺灣大學	2008	A 50 GHz Divide-by-4 Injection Lock Frequency Divider Using Matching Method	Chuang, Mei-Chen; Kuo, Jhe-Jia; Wang, Chi-Hsueh; Wang, Huei
國立交通大學	2017-04-21T06:55:43Z	A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting	Chen, Po-Hung; Wu, Chung-Shiang; Lin, Kai-Chun
國立臺灣大學	2009	A 50 to 70 GHz power amplifier using 90 nm CMOS technology	Kuo, Jing-Lin; Tsai, Zuo-Min; Lin, Kun-You; Wang, Huei
臺大學術典藏	2009	A 50 to 70 GHz power amplifier using 90 nm CMOS technology	Kuo, J.-L.;Tsai, Z.-M.;Lin, K.-Y.;Wang, H.; Kuo, J.-L.; Tsai, Z.-M.; Lin, K.-Y.; Wang, H.; HUEI WANG; KUN-YOU LIN
國立臺灣大學	2007	A 50 to 94-GHz CMOS SPDT Switch Using Traveling-Wave Concept	Chao, S.-F.; Wang, H.; Su, C.-Y.; Chern, J. G. J.

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