| 國立成功大學 |
2007-07-16 |
Layout design for flexible manufacturing systems considering single-loop directional flow patterns
|
Yang, Taho; Peters, Brett A.; Tu, Mingan |
| 國立交通大學 |
2014-12-08T15:26:21Z |
Layout design of high-quality SOI varactor
|
Chen, HY; Chen, KM; Huang, GW; Huang, CH; Yang, TH; Chang, CY |
| 國立交通大學 |
2014-12-08T15:26:43Z |
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process
|
Ker, MD; Chuang, CH; Lo, WY |
| 國立交通大學 |
2014-12-08T15:43:05Z |
Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit
|
Ker, MD; Chen, TY |
| 國立臺灣科技大學 |
2003 |
Layout Improvement for the Facility Design of Semiconductor Fabrication
|
Chen, J. C. ; Peng, G. M. ; Sun, C. J. ; Wang, J. J. ; Chang, P. F. ; Dai, R. D. |
| 中原大學 |
2003-03 |
Layout Improvement for the Facility Design of Semiconductor Fabrication
|
J. C. Chen;G. M. Peng;C. J. Sun;J. J. Wang;P. F. Chang;R. D. Dai; |
| 國立臺灣科技大學 |
2004 |
Layout Improvement for Wafer Fabrication Plants
|
Chen, J. C. ; Yang, R. T. ; Peng, K. M. ; Wang, C. C. |
| 中原大學 |
2004-03 |
Layout Improvement for Wafer Fabrication Plants
|
J. C. Chen;R. T. Yang;K. M. Peng;C. C. Wang; |
| 臺大學術典藏 |
2022-09-21T23:30:15Z |
Layout of 1.50-inch, 3207-ppi oled display with oslsi/silsi structure capable of division driving fabricated through vlsi process with side-by-side patterning by photolithography
|
Saito, Toshihiko; Mizuguchi, Toshiki; Okamoto, Yuki; Ito, Minato; Toyotaka, Kouhei; Kozuma, Munehiro; Matsuzaki, Takanori; Kobayashi, Hidetomo; Onuki, Tatsuya; Hiura, Yoshikazu; Hodo, Ryota; Sasagawa, Shinya; Kunitake, Hitoshi; Nakamura, Daiki; Sato, Hitomi; Kimura, Hajime; Wu, Chih Chiang; Yoshida, Hiroshi; Chen, Min Cheng; MING-HAN LIAO; Chang, Shou Zen; Yamazaki, Shunpei |
| 國立交通大學 |
2017-04-21T06:49:53Z |
Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
|
Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:51Z |
Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces
|
Chang, WJ; Ker, MD |
| 中原大學 |
1998-11-10 |
Layout structure for improving resistance uniformity of a polysilicon resistor
|
Shen-Wen Cheng;Chun-Lin Cheng |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Layout Styles to Improve CDM ESD Robustness of Integrated Circuits in 65-nm CMOS Process
|
Ker, Ming-Dou; Lin, Chun-Yu; Chang, Tang-Long |
| 國立臺灣大學 |
1985-09 |
Layout System Vol. 1:Computer-Aided VLSI Routing Design
|
Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立臺灣大學 |
1985 |
Layout System Vol. 2:Symbolic Layout and Circuit Compaction for CMOS IC Design
|
Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立臺灣大學 |
1985-09 |
Layout System Vol. 3:Design and Implementation of a Design Rule Checking System for VLSI Design
|
Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-09 |
Layout System Vol. 4:an Automatic Placement System for VLSI Layouts
|
Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立交通大學 |
2014-12-08T15:25:40Z |
Layout techniques for on-chip interconnect inductance reduction
|
Tu, SW; Jou, JY; Chang, YW |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Layout techniques for on-chip interconnect inductance reduction
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 義守大學 |
2011 |
Layout 設計與電磁相容之研究
|
陳安吉; An-Chi chen |
| 國立中山大學 |
2006-08 |
Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis
|
X.L. Li;S.J. Wang;K.S.M. Li |
| 國立中山大學 |
2006-08 |
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage
|
K.L. Peng;S.J. Wang;K.S.M. Li |
| 國立交通大學 |
2019-10-05T00:09:48Z |
Layout-Based Dual-Cell-Aware Tests
|
Wu, Tse-Wei; Lee, Dong-Zhen; Wu, Kai-Chiang; Huang, Yu-Hao; Chen, Ying-Yen; Chen, Po-Lin; Chern, Mason; Lee, Jih-Nung; Kao, Shu-Yi; Chao, Mango C. -T. |
| 國立交通大學 |
2017-04-21T06:56:48Z |
Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults-From Device to Circuit Level
|
Huang, Hsuan-Ming; Wen, Charles H. -P. |
| 臺大學術典藏 |
2018-09-10T15:33:11Z |
Layout-Dependent Effects-Aware Analytical Analog Placement
|
Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG |
