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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 575301-575310 / 2348617 (共234862頁)
<< < 57526 57527 57528 57529 57530 57531 57532 57533 57534 57535 > >>
每頁顯示[10|25|50]項目
| 中華大學 |
2006 |
Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
Memory-Efficiency Multiplierless VLSI Architecture for 2-D DWT Using 9/7 Wavelet Filter
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Memory-Efficiency Multiplierless VLSI Architecture for 2-D DWT Using 9/7 Wavelet Filter
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
Memory-Efficient and Fast Architectures for Forward and Inverse DCT with Multiplierless Operation
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Memory-Efficient and Fast Architectures for Forward and Inverse DCT with Multiplierless Operation,
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謝曜式; Shieh, Yaw-Shih |
| 國立聯合大學 |
2007 |
Memory-Efficient and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation
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Tze-Yun Sung, Hsi-Chin Hsin |
| 中華大學 |
2007 |
Memory-Efficient and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2007 |
Memory-EfficiEnt and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2007 |
Memory-Efficient and High-Performance Parallel-Pipelined Architectures for 5/3 Forward and Inverse Discrete Wavelet Transform
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宋志雲; Sung, Tze-Yun |
顯示項目 575301-575310 / 2348617 (共234862頁)
<< < 57526 57527 57528 57529 57530 57531 57532 57533 57534 57535 > >>
每頁顯示[10|25|50]項目
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