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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 91451-91460 / 2348419 (共234842頁)
<< < 9141 9142 9143 9144 9145 9146 9147 9148 9149 9150 > >>
每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri; Lee, Jri |
| 國立臺灣大學 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri |
| 臺大學術典藏 |
2018-09-10T06:03:22Z |
A 20-Gb/s Adaptive Equalizer in 0.13 μm CMOS Technology
|
Jri Lee; JRI LEE |
| 國立臺灣大學 |
2006 |
A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology
|
Lee, Jri |
| 國立臺灣大學 |
2008 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
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Lee, Jri; Liu, Mingchung |
| 國立臺灣大學 |
2008-03 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
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Lee, Jri; Liu, M. |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
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Lee, Jri;Wu, Ke-Chung; Lee, Jri; Wu, Ke-Chung; JRI LEE |
| 國立交通大學 |
2014-12-08T15:34:51Z |
A 20-Gb/s Optical Receiver with Integrated Photo Detector in 40-nm CMOS
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Huang, Shih-Hao; Chen, Wei-Zen |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-Gb/s transmitter with adaptive preemphasis in 65-nm CMOS technology
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Kao, S.-Y.;Liu, S.-I.; Kao, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 國立交通大學 |
2019-04-02T06:04:28Z |
A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery
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Lee, Yuan-Sheng; Chen, Wei-Zen |
顯示項目 91451-91460 / 2348419 (共234842頁)
<< < 9141 9142 9143 9144 9145 9146 9147 9148 9149 9150 > >>
每頁顯示[10|25|50]項目
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