| 國立臺灣大學 |
2008 |
A 2.88mm2 50M-intersections/s ray-triangle intersection unit for interactive ray tracing
|
Chang, Chen-Haur; Lee, Chuan-Yiu; Chien, Shao-Yi |
| 臺大學術典藏 |
2018-09-10T07:03:47Z |
A 2.88mm2 50M-intersections/s ray-triangle intersection unit for interactive ray tracing
|
Chang, C.-H.; Lee, C.-Y.; Chien, S.-Y.; SHAO-YI CHIEN |
| 臺大學術典藏 |
2018-09-10T07:36:39Z |
A 2.89mW 50GOPS 16 × 16 16-core MIMO sphere decoder in 90nm CMOS
|
Yang, C.-H.;Markovic, D.; Yang, C.-H.; Markovic, D.; CHIA-HSIANG YANG |
| 國立臺灣大學 |
1998 |
A 2.9-Kilobase noncoding nuclear RNA function in the establishment of persistent Hz-1 viral infection
|
Chao, Yu-Chan; Lee, Song-Tay; Chang, Ming-Chuan; Chen, Hong-Hwa; Chen, Shih-Shun; Wu, Tzong-Yuan; Liu, Fu-Hw; Hsu, Err-Lieh; Hou, Roger F. |
| 中原大學 |
1998 |
A 2.9-kilobase noncoding nuclear RNA functions in the establishment of persistent Hz-1 viral infection
|
Yu-Chan Chao;Song-Tay Lee;Ming-Chuan Chang;Hong-Hwa Chen;Shih-Shun Chen;Tzong-Yuan Wu;Fu-Hwa Liu;Err-Lieh Hsu;Roger F. Hou |
| 南台科技大學 |
1998-05 |
A 2.9-Kilobase noncoding nuclear RNA functions in the establishment of persistent Hz-1 viral infection.
|
李松泰; Yu-Chan Chao; Song-Tay Lee; Ming-Chuan Chang; Hong-Hwa Chen; Shih-Shun Chen; Tzong-Yuan Wu; Fu-Hwa Liu; Err-Lieh Hsu; Roger F. Hou |
| 臺大學術典藏 |
2020-06-11T06:25:37Z |
A 20 GHz power amplifier with IM3 distortion cancellation by load-split derivative superposition
|
Kao, K.-Y.;Lin, H.-Y.;Lin, K.-Y.; Kao, K.-Y.; Lin, H.-Y.; Lin, K.-Y.; KUN-YOU LIN |
| 臺大學術典藏 |
2020-06-11T06:31:42Z |
A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process
|
Jen, Y.-N.;Tsai, J.-H.;Peng, C.-T.;Huang, T.-W.; Jen, Y.-N.; Tsai, J.-H.; Peng, C.-T.; Huang, T.-W.; TIAN-WEI HUANG |
| 元智大學 |
2009-01 |
A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-µm CMOS process
|
蔡政翰; Yung-Nien Jen; Chung-Te Peng; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:44Z |
A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process
|
Yung-Nien Jen; Jeng-Han Tsai; Chung-Te Peng; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:44Z |
A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process
|
Yung-Nien Jen; Jeng-Han Tsai; Chung-Te Peng; Tian-Wei Huang |
| 淡江大學 |
2005-03 |
A 20 Years Overview and Prospect of Interpretive Research in Taiwan: 1984-2003
|
陳維立; Wu, H. C.; Chen, W. J. |
| 臺大學術典藏 |
2021-09-02T00:05:04Z |
A 20-43 GHz Low Noise GaAs Downconverter with Gbps Data-Links for Full 5G K/Ka-Band Backhauls
|
Chen C.-N;Kuo T.-Y;Wang H.; Chen C.-N; Kuo T.-Y; Wang H.; HUEI WANG |
| 臺大學術典藏 |
2021-03-12T08:41:03Z |
A 20-Gb/s 1: 2 demultiplexer with capacitive-splitting current-mode-logic latches
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
| 國立臺灣大學 |
2007 |
A 20-Gb/s 1:2 Demultiplexer with capacitive-splitting current-mode-logic latches
|
Chien, Jun-Chau; Lu, Liang-Hung |
| 國立臺灣大學 |
2005-06 |
A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-/spl mu/m CMOS technology
|
Lee, Jri; Ding, Jian-Yu; Cheng, Tuan-Yi |
| 臺大學術典藏 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri; Lee, Jri |
| 國立臺灣大學 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri |
| 臺大學術典藏 |
2018-09-10T06:03:22Z |
A 20-Gb/s Adaptive Equalizer in 0.13 μm CMOS Technology
|
Jri Lee; JRI LEE |
| 國立臺灣大學 |
2006 |
A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology
|
Lee, Jri |
| 國立臺灣大學 |
2008 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, Mingchung |
| 國立臺灣大學 |
2008-03 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, M. |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
|
Lee, Jri;Wu, Ke-Chung; Lee, Jri; Wu, Ke-Chung; JRI LEE |
| 國立交通大學 |
2014-12-08T15:34:51Z |
A 20-Gb/s Optical Receiver with Integrated Photo Detector in 40-nm CMOS
|
Huang, Shih-Hao; Chen, Wei-Zen |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-Gb/s transmitter with adaptive preemphasis in 65-nm CMOS technology
|
Kao, S.-Y.;Liu, S.-I.; Kao, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
