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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 92161-92170 / 2346788 (共234679頁)
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| 元智大學 |
2003-06 |
A 5.8-GHz high efficient, low power, low phase noise CMOS VCO for IEEE 802.11a
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吳紹懋; Ron-Yi Liu; Wei-Liang Chen |
| 國立臺灣科技大學 |
2016 |
A 5.8-GHz radar sensor chip in 0.18-μm CMOS for non-contact vital sign detection
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Huang, J.-K;Tseng, C.-H. |
| 臺大學術典藏 |
2002-06 |
A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology
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Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang; Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang |
| 國立臺灣大學 |
2002-06 |
A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology
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Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang |
| 元智大學 |
2002-08 |
A 5.8Ghz CMOS RF Image-Rejection Receiver Front-end using 90-degree Delayed-Lock Loop
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吳紹懋; Ron-Yi Liu; Sin-Yu Chen |
| 元智大學 |
2003-10 |
A 5.8GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications
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吳紹懋; 劉榮宜; 陳威良 |
| 臺大學術典藏 |
2018-09-10T08:14:45Z |
A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs
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Yang, C.-H.;Yu, T.-H.;Markovi?, D.; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG |
| 國立交通大學 |
2019-09-02T07:45:41Z |
A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems
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Ng, Chee-Kit; Lin, Yu-Chun; Jou, Shyh-Tye |
| 國立交通大學 |
2019-10-05T00:09:47Z |
A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems
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Ng, Chee-Kit; Chiu, Kang-Lun; Lin, Yu-Chun; Jou, Shyh-Jye |
| 國立臺灣大學 |
2008 |
A 50 GHz Divide-by-4 Injection Lock Frequency Divider Using Matching Method
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Chuang, Mei-Chen; Kuo, Jhe-Jia; Wang, Chi-Hsueh; Wang, Huei |
顯示項目 92161-92170 / 2346788 (共234679頁)
<< < 9212 9213 9214 9215 9216 9217 9218 9219 9220 9221 > >>
每頁顯示[10|25|50]項目
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