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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 256316-256325 / 2346288 (共234629頁)
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| 臺大學術典藏 |
2018-09-10T04:59:56Z |
Circuit Partition and Reordering Technique for Low Power IP
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Kun-lin Tsai,; Shanq-jang Ruan,; Chun-ming Huang,; Edwin Naroska,; Feipei Lai,; FEI-PEI LAI |
| 國立交通大學 |
2014-12-08T15:25:06Z |
Circuit performance degradation of sample-and-hold amplifier due to gate-oxide overstress in a 130-nm CMOS process
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Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:12:29Z |
Circuit performance degradation of switched-capacitor circuit with bootstrapped technique due to gate-oxide overstress in a 130-nm CMOS process
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Chen, Jung-Sheng; Ker, Ming-Dou |
| 臺大學術典藏 |
2018-09-10T04:33:46Z |
Circuit placement in arbitrarily shaped regions using neural network
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Chang, Ray-I; Hsiao, Pei-Yung; RAY-I CHANG |
| 國立交通大學 |
2014-12-08T15:28:00Z |
CIRCUIT PLACEMENT IN ARBITRARILY-SHAPED REGIONS USING NEURAL-NETWORK
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CHANG, RI; HSIAO, PY |
| 國立高雄第一科技大學 |
2011.08 |
CIRCUIT RELIABILITY EVALUATION USING TWO-STAGE COMPLEX NETWORK ANALYSIS
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Huang, Ming-Chih;Chen, Ming-Huei;Chen, Hao-Hui;Ting, Yi-Chuan;Huang, Hong-Hsin |
| 淡江大學 |
2014-08 |
Circuit Simulation for Solar Power Maximum Power Point Tracking with Different Buck-Boost Converter Topologies
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蕭照焜; 李珉毅; 魏煜宸; 陳柏志 |
| 淡江大學 |
2014-03 |
Circuit Simulation for Solar Power Maximum Power Point Tracking with Different Buck-Boost Converter Topologies
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蕭照焜;李珉毅;魏煜宸;陳柏志 |
| 國立交通大學 |
2014-12-08T15:24:42Z |
Circuit Solutions on ESD Protection Design for Mixed-Voltage I/O Buffers in Nanoscale CMOS
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Ker, Ming-Dou; Wang, Chang-Tzu |
| 義守大學 |
1999-07 |
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS
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Ker, Ming-Dou ; Wang, Chang-Tzu |
顯示項目 256316-256325 / 2346288 (共234629頁)
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每頁顯示[10|25|50]項目
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