| 國立成功大學 |
2022 |
Hardness and approximation for the star p-Hub Routing Cost Problem in metric graphs
|
Yeh, H.-P.;Lu, W.;Chen, L.-H.;Hung, L.-J.;Klasing, R.;Hsieh, S.-Y. |
| 臺大學術典藏 |
1992 |
Hardness and Fracture Toughness of Y123/Ag Composite
|
Wu, J. M.; Tuan, Wei-Hsing; 段維新; Wu, J. M.; Tuan, Wei-Hsing |
| 國立臺灣大學 |
1992 |
Hardness and Fracture Toughness of Y123/Ag Composite
|
段維新; Wu, J. M.; Tuan, Wei-Hsing; Wu, J. M. |
| 臺大學術典藏 |
2019-09-09T00:54:21Z |
Hardness and strength enhancements of CoCrFeMnNi high-entropy alloy with Nd doping
|
CHENG-PING WANG;Li, Tsung Hsiung;Jang, Jason Shian Ching;CHUN-HWAY HSUEH;Li, Chia Lin;Liao, Yi Chia; Liao, Yi Chia; Li, Chia Lin; CHUN-HWAY HSUEH; Jang, Jason Shian Ching; Li, Tsung Hsiung; CHENG-PING WANG |
| 國立成功大學 |
2024 |
Hardness and Approximation for the Star β -Hub Routing Cost Problem in Δβ -Metric Graphs
|
Tsai;M, -S.;Hsieh;S, -Y.;Hung;L, -J. |
| 國立臺灣海洋大學 |
2006-04 |
Hardness Enhancement in Nanocrystalline Tantalum Thin Films
|
M. Zhang;B. Yang;J. P. Chu;T. G. Nieh |
| 臺大學術典藏 |
2018-09-10T08:11:52Z |
Hardness of comparing two run-length encoded strings
|
Chen, K.-Y.;Hsu, P.-H.;Chao, K.-M.; Chen, K.-Y.; Hsu, P.-H.; Chao, K.-M.; KUN-MA0 CHAO |
| 元智大學 |
2014-04-25 |
Hardness of learning abelian loops in sublinear time
|
Yu-Han Cheng (鄭又涵); Ching-Lueh Chang |
| 元智大學 |
2014-1-1 |
Hardness of learning loops, monoids, and semirings
|
Ching-Lueh Chang |
| 中華大學 |
2009 |
Hardness, Abrasion, ans Slip-Resistance of New and Used Shoes
|
李開偉; Li, Kai Way |
| 國立臺灣科技大學 |
2012 |
Hardness, yield strength, and plastic flow in thin film metallic-glass
|
Ye, J.C.;Chu, J.P.;Chen, Y.C.;Wang, Q.;Yang, Y. |
| 國立政治大學 |
2003 |
Hardships of student life
|
Tzou, Byron; 鄒念祖 |
| 臺大學術典藏 |
2020-06-11T06:45:58Z |
Hardware accelerated aerial image simulation by FPGA
|
Jamleh, H.;Chung-Ping Chen, C.; Jamleh, H.; Chung-Ping Chen, C.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T08:18:46Z |
Hardware Accelerated Embedded System for Face Detection and Facial Expression Recognition
|
Ren C. Luo;S H,Liu; Ren C. Luo; S H,Liu; REN-CHYUAN LUO |
| 臺大學術典藏 |
2018-09-10T08:19:21Z |
Hardware Accelerated XML Parsers with Well Form Checkers and Abstract Classification Tables
|
Sheng-De Wang;Chun-Wei Chen;Michael Pan;n Chih-Hao Hsu; Sheng-De Wang; Chun-Wei Chen; Michael Pan; n Chih-Hao Hsu; SHENG-DE WANG |
| 臺大學術典藏 |
2018-09-10T09:42:23Z |
Hardware acceleration for proton beam Monte Carlo simulation
|
Tsai, M.-Y.;Hung, S.-H.; Tsai, M.-Y.; Hung, S.-H.; SHIH-HAO HUNG |
| 臺大學術典藏 |
2020-05-04T08:04:36Z |
Hardware acceleration for proton beam Monte Carlo simulation.
|
SHIH-HAO HUNG; Hung, Shih-Hao; Tsai, Min-Yu; Tsai, Min-Yu;Hung, Shih-Hao |
| 淡江大學 |
2009-06-26 |
Hardware accelerator design for image process
|
李世安 |
| 淡江大學 |
2012-08 |
Hardware accelerator design for image processing
|
Li, Shih-an; Wong, Ching-chang; Yang, Ching-yang; Chen, Li-feng |
| 淡江大學 |
2012-08 |
Hardware accelerator design for image processing
|
Li, Shih-An; Wong, Ching-Chang; Yang, Ching-Yang; Chen, Li-Feng |
| 淡江大學 |
2012-08 |
Hardware Accelerator Design for Image Processing
|
Li, S.A.; Wong, C.C.; Yang, C.Y.; Chen, L.F. |
| 淡江大學 |
2012-08-20 |
Hardware accelerator design for image processing
|
Li, S.A.;Wong, C.C.;Yang, C.Y.;Chen, L.F. |
| 國立高雄第一科技大學 |
2005.04 |
Hardware Accelerator for Vector Quantization by Using Pruned Look-Up Table
|
Wang, Pi-Chung;Lee, Chun-Liang;Chang, Hung-Yi;Chen, Tung-Shou; 張弘毅 |
| 國立高雄第一科技大學 |
2005-05 |
Hardware Accelerator for Vector Quantization by Using Pruned Look-Up Table
|
Wang, Pi-Chung;Lee, Chun-Liang;Chang, Hung-Yi;Chen, Tung-Shou; 張弘毅 |
| 南台科技大學 |
2017 |
Hardware and Software Cooperative Control System for Die-Cutting Machine Tool
|
Su, Chia-Hsiang; Lin, Horng-Horng; Liu, Yu-Shih |
| 國立臺灣大學 |
2008 |
Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies
|
Chang, Chen-Haur; Lee, Chuan-Yiu; Chien, Shao-Yi |
| 臺大學術典藏 |
2018-09-10T07:03:44Z |
Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies
|
Chang, Chen-Haur; Lee, Chuan-Yiu; Chien, Shao-Yi; SHAO-YI CHIEN |
| 臺大學術典藏 |
2004-05 |
Hardware architecture design for H.264/AVC intra frame coder
|
Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee; Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Hardware architecture design for H.264/AVC intra frame coder
|
Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:21Z |
Hardware architecture design for H.264/AVC intra frame coder
|
Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2003-05 |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Hsieh, Bing-Yu; Chen, Liang-Gee; Wang, Tu-Chih; Huang, Yu-Wen; Wang, Tu-Chih; Hsieh, Bing-Yu; Chen, Liang-Gee; Huang, Yu-Wen |
| 國立臺灣大學 |
2003-05 |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Huang, Yu-Wen; Wang, Tu-Chih; Hsieh, Bing-Yu; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Huang, Y.-W.; Wang, T.-C.; Hsieh, B.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2004-08 |
Hardware architecture design for visual processing: present and future
|
Tseng, Po-Chih; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-08 |
Hardware architecture design for visual processing: present and future
|
Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:20Z |
Hardware architecture design for visual processing: Present and future
|
Tseng, P.-C.; Chen, L.-G.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2006-01 |
Hardware architecture design of an H.264/AVC video codec
|
Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee; Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee |
| 國立臺灣大學 |
2006-01 |
Hardware architecture design of an H.264/AVC video codec
|
Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T05:50:30Z |
Hardware architecture design of an H.264/AVC video codec
|
Chen, T.-C.; Lian Jr.; C.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2011 |
Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation
|
Hsu, Kung-Yen; Chien, Shao-Yi |
| 臺大學術典藏 |
2018-09-10T08:42:33Z |
Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation
|
Hsu, Kung-Yen;Chien, Shao-Yi; Hsu, Kung-Yen; Chien, Shao-Yi; SHAO-YI CHIEN |
| 臺大學術典藏 |
2018-09-10T09:22:24Z |
Hardware architecture design of hybrid distributed video coding with frame level coding mode selection
|
Chiu, C.-C.; Wu, H.-F.; Chien, S.-Y.; Lee, C.-H.; Somayazulu, V.S.; Chen, Y.-K.; SHAO-YI CHIEN |
| 國立臺灣大學 |
2005-08 |
Hardware architecture design of video compression for multimedia communication systems
|
Chien, Shao-Yi; Huang, Yu-Wen; Chen, Ching-Yeh; Chen, Homer H.; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Hardware architecture design of video compression for multimedia communication systems
|
Chen, Liang-Gee; Chen, Homer H.; Chen, Ching-Yeh; Huang, Yu-Wen; LIANG-GEE CHEN; Chien, Shao-Yi; Chien, Shao-Yi; LIANG-GEE CHEN |
| 臺大學術典藏 |
2007-04-19T04:02:59Z |
Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile
|
Chen, Liang-Gee;Chien, Shao-Yi;Huang, Yu-Wen;Chen, Ching-Yeh;Chao, Wei-Min; Chen, Ching-Yeh; Chien, Shao-Yi; Chao, Wei-Min; Huang, Yu-Wen; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile
|
Chen, Ching-Yeh; Chien, Shao-Yi; Chao, Wei-Min; Huang, Yu-Wen; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:19Z |
Hardware architecture for global motion estimation for MPEG-4 advanced simple profile
|
Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立交通大學 |
2014-12-08T15:09:16Z |
Hardware Architecture for High-Performance Regular Expression Matching
|
Lee, Tsern-Huei |
| 中華大學 |
2011 |
Hardware Architecture of Real-Time Stereoscopic Image Generation from Depth Map
|
鄭芳炫; Cheng, Fang Hsuan |
| 臺大學術典藏 |
2018-09-10T06:30:49Z |
Hardware architecture to realize multi-layer image processing in real-time
|
Fu, Li-Chen; Lu Chieh-Lun; LI-CHEN FU |
