| 國立臺灣大學 |
2007 |
Hardware Architecture to Realize Multi-layer Image Processing in Real-time
|
Fu, Li-Chen; Lu Chieh-Lun |
| 亞洲大學 |
2007-12-20 |
Hardware Context Switching Methodology for Dynamically Partially Reconfigurable Systems
|
Trong-Yen Lee; Che-Cheng Hu; Li-Wen Lai; Chia-Chun Tsai and Rong-Shue Hsiao |
| 國立成功大學 |
2016-06 |
Hardware Design and Implementation for Empirical Mode Decomposition
|
Chen, Pei-Yin; Lai, Yen-Chen; Zheng, Ju-Yang |
| 國立臺灣科技大學 |
2017 |
Hardware design for statistical network traffic classifiers
|
Lu, C.-N;Lai, Y.-C;Huang, C.-Y;Lin, Y.-D. |
| 國立交通大學 |
2018-08-21T05:56:54Z |
Hardware Design for Statistical Network Traffic Classifiers
|
Lu, Chun-Nan; Lai, Yuan-Cheng; Huang, Chun-Ying; Lin, Ying-Dar |
| 國立彰化師範大學 |
1995 |
Hardware Design of A Real-Time Petri Net Model for Real-Time Tasks
|
黃其泮;何正信 |
| 國立成功大學 |
2018-11 |
Hardware Design of an Energy-Efficient High-Throughput Median Filter
|
Lin;Shih-Hsiang;Chen;Pei-Yin;Lin;Chang-Hsing |
| 國立臺灣科技大學 |
2010 |
Hardware design of features extraction using wavelet packet method for intelligent diagnostic system
|
Huang C.-C.; Huang C.-H.; Tsao Y.-M.; Huang S.-C.; Huang H.-L. |
| 國立成功大學 |
2017-08-1 |
Hardware Design of Low-Power High-Throughput Sorting Unit
|
Lin;Shih-Hsiang;Chen;Pei-Yin;Lin;Yu-Ning |
| 國立臺灣大學 |
1997-06 |
Hardware efficient design of filter banks for video coding
|
Wu, Po-Cheng; Chen, Liang-Gee; Liu, Yuan-Chen; Lai, Yeong-Kang |
| 臺大學術典藏 |
2018-09-10T06:20:27Z |
Hardware efficient design of filter banks for video coding
|
Wu, Po-Cheng; Chen, Liang-Gee; Liu, Yuan-Chen; Lai, Yeong-Kang; LIANG-GEE CHEN |
| 國立交通大學 |
2014-12-08T15:03:36Z |
Hardware efficient skip mode detection for H.264/AVC
|
Lin, Chia-Chun; Lin, Yu-Kun; Chang, Tian-Sheuan |
| 國立交通大學 |
2014-12-08T15:27:17Z |
Hardware efficient transform designs with cyclic formulation and subexpression sharing
|
Chang, TS; Jen, CW |
| 臺大學術典藏 |
2018-09-10T05:57:28Z |
Hardware enhanced mining for association rules
|
Liu, W.-C.; Liu, K.-H.; Chen, M.-S.; MING-SYAN CHEN |
| 國立臺灣大學 |
2010 |
Hardware Equivalence and Property Verification
|
Jiang, Jie-Hong R.; Villa, Tiziano |
| 臺大學術典藏 |
2018-09-10T08:19:13Z |
Hardware Equivalence and Property Verification
|
Jie-Hong R. Jiang;Tiziano Villa; Jie-Hong R. Jiang; Tiziano Villa; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:11Z |
Hardware Equivalence and Property Verification.
|
Jiang, Jie-Hong Roland;Villa, Tiziano;Crama, Yves;Hammer, Peter L.; Jiang, Jie-Hong Roland; Villa, Tiziano; Crama, Yves; Hammer, Peter L.; JIE-HONG JIANG |
| 元智大學 |
2020/12/3 |
Hardware for Controlling a Dynamic Lighting System
|
Apoorv Mahesh Chaudhari; Chiung Reng Tai; Nafia AL-Mutawaly; Hsu Y.-L.; Jonathon David White |
| 國立成功大學 |
2008-04 |
Hardware implementation for a genetic algorithm
|
Chen, Pei-Yin; Chen, Ren-Der; Chang, Yu-Pin; Shieh, Leang-San; Malki, Heidar A. |
| 國立彰化師範大學 |
2008-04 |
Hardware Implementation for a Genetic Algorithm
|
Chen, Pei-Yin; Chen, Ren-Der; Chang, Yu-Pin; Shieh, Leang-San; Malki, Heidar A. |
| 國立臺灣大學 |
2004-05-31 |
Hardware Implementation Issues on Viterbi Decoder
|
Wu, Meng-Hau |
| 國立成功大學 |
2017 |
Hardware implementation of a distributed pv system based on the central operation of the MPPT algorithm
|
Chao, R.-M.;Jhang, Jhang J.-C.;Wang, I.-K.;Hsu, S.-C. |
| 國立成功大學 |
2013-08 |
Hardware Implementation of a Fast and Efficient Haze Removal Method
|
Shiau, Yeu-Horng; Yang, Hung-Yu; Chen, Pei-Yin; Chuang, Ya-Zhu |
| 中華大學 |
2007 |
Hardware Implementation of a High-Speed (32, 24, 4) RS Decoder
|
陳棟洲; Chen, Tung-Chou |
| 國立彰化師範大學 |
2007-12 |
Hardware Implementation of a High-Speed (32, 24, 4) RS Decoder
|
Chen, Tung-Chou; Tasi, Ming-Hsi |
