| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
A 1.5-mW, 23.6% frequency locking range,24-GHz injection-locked frequency divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang |
| 臺大學術典藏 |
2006-05 |
A 1.5-V 10-ppm//spl deg/C 2nd-order curvature-compensated CMOS bandgap reference with trimming
|
Hsiao, Sen-Wen; Huang, Yen-Chih; Liang, David; Chen, H.W.K.; Chen, Hsin-Shu; Hsiao, Sen-Wen; Huang, Yen-Chih; Liang, David; Chen, H.W.K.; Chen, Hsin-Shu |
| 國立臺灣大學 |
2006-05 |
A 1.5-V 10-ppm//spl deg/C 2nd-order curvature-compensated CMOS bandgap reference with trimming
|
Hsiao, Sen-Wen; Huang, Yen-Chih; Liang, David; Chen, H.W.K.; Chen, Hsin-Shu |
| 國立交通大學 |
2014-12-08T15:48:10Z |
A 1.5-V 3 similar to 10-GHz 0.18-mu m CMOS Frequency Synthesizer for MB-OFDM UWB Applications
|
Huang, Zue-Der; Kuo, Fong-Wei; Wang, Wen-Chieh; Wu, Chung-Yu |
| 臺大學術典藏 |
1999-05 |
A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation
|
J. H. Lou; J. B. Kuo; JAMES-B KUO |
| 國立臺灣大學 |
1999 |
A 1.5-V CMOS all-N-logic true-single-phase bootstrappeddynamic-logic circuit suitable for low supply voltage and high-speedpipelined system operation
|
Lou, J.H.; Kuo, J.B. |
| 國立交通大學 |
2014-12-08T15:47:31Z |
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
|
Tseng, YK; Wu, CY |
| 國立交通大學 |
2019-04-02T05:59:23Z |
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
|
Tseng, YK; Wu, CY |
| 國立臺灣科技大學 |
2009 |
A 1.5-V transformer-based ultra-wideband LNA chip design
|
Huang J.-F.; Shie P.-J.; Liu R.-Y. |
| 國立交通大學 |
2014-12-08T15:27:05Z |
A 1.5-V, 2.4GHz CMOS low-noise amplifier
|
Yang, JN; Lee, CY; Hsu, TY; Hsu, TR; Wang, CC |
| 臺大學術典藏 |
2021-09-02T00:04:03Z |
A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots
|
Chung C;Yang C.-H.; Chung C; Yang C.-H.; CHIA-HSIANG YANG |
| 國立臺灣大學 |
2009 |
A 1.5GHz all-digital spread spectrum clock generator
|
Lin, Sheng-You; Liu, Shen-Iuan |
| 臺大學術典藏 |
2018-09-10T07:41:58Z |
A 1.5GHz all-digital spread spectrum clock generator
|
Sheng-You Lin;Shen-Iuan Liu; Sheng-You Lin; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T07:41:58Z |
A 1.5GHz phase-locked loop with leakage current suppression in 65nm CMOS
|
Jung-Yu Chang;Shen-Iuan Liu; Jung-Yu Chang; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立交通大學 |
2014-12-08T15:20:50Z |
A 1.5V 7.5uW Programmable Gain Amplifier for Multiple Biomedical Signal Acquisition
|
Kao, Shuo-Ting; Lu, Hungwen; Su, ChauChin |
| 國立交通大學 |
2014-12-08T15:27:27Z |
A 1.5V differential cross-coupled bootstrapped BiCMOS logic
|
Tseng, YK; Wu, CY |
| 臺大學術典藏 |
2021-02-26T08:42:04Z |
A 1.5£gJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots
|
Chung, C.; Yang, C.-H.; CHIA-HSIANG YANG |
| 國立臺灣大學 |
2008 |
A 1.5–9.6 GHz Monolithic Active Quasi-Circulator in 0.18μm CMOS Technology
|
Shin, Shih-Chieh; Huang, Jhih-Yu; Lin, Kun-You; Wang, Huei |
| 國立成功大學 |
2021 |
A 1.6-Gs/s 8b flash-SAR time-interleaved ADC with top-plate residue based gain calibration
|
Hsu, C.-W.;Chang, S.-J. |
| 臺大學術典藏 |
2018-09-10T08:18:16Z |
A 1.62/2.7-Gb/s adaptive transmitter with two-tap preemphasis using a propagation-time detector
|
Shih-Yuan Kao;Shen-Iuan Liu; Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2021-11-21T23:19:02Z |
A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS
|
Liu, Yu Tung; Kung, Chu King; Hsieh, Ming Hang; Wang, Hsiu Wen; CHUN-PIN LIN; Yu, Chao Yang; Chen, Chi Shi; TZI-DAR CHIUEH |
| 臺大學術典藏 |
2022-02-21T23:30:47Z |
A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS
|
Liu, Yu Tung; Kung, Chu King; Hsieh, Ming Hang; Wang, Hsiu Wen; CHUN-PIN LIN; Yu, Chao Yang; Chen, Chi Shi; TZI-DAR CHIUEH |
| 國立交通大學 |
2014-12-08T15:41:18Z |
A 1.69 Gb/s Area-Efficient AES Crypto Core with Compact On-the-fly Key Expansion Unit
|
Liu, Po-Chun; Chang, Hsie-Chia; Lee, Chen-Yi |
| 元智大學 |
2009-06 |
A 1.7-mW, 14.4% Frequency Tuning, 24GHz VCO with Current-Reused Structure Using 0.18-um CMOS Technology
|
蔡政翰; Yen-Hung Kuo; Tian-Wei Huang |
| 元智大學 |
2009-06 |
A 1.7-mW, 14.4% Frequency Tuning, 24GHz VCO with Current-Reused Structure Using 0.18-um CMOS Technology
|
蔡政翰; Yen-Hung Kuo; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:46Z |
A 1.7-mW, 14.4% Frequency Tuning,24GHz VCO with Current-Reused Structure Using 0.18-μm CMOS Technology
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang |
| 臺大學術典藏 |
2018-09-10T07:42:57Z |
A 1.7-mW, 16.8% Frequency Tuning, 24-GHz Transformer-Based LC-VCO using 0.18-um CMOS Technology
|
Yen-Hung Kuo;Jeng-Han Tsai;Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; TIAN-WEI HUANG |
| 國立交通大學 |
2014-12-08T15:26:52Z |
A 1.75GHz inductor-less CMOS low noise amplifier with high-Q active inductor load
|
Yang, JN; Cheng, YC; Hsu, TY; Hsu, TR; Lee, CY |
| 國立交通大學 |
2014-12-08T15:24:51Z |
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
|
Chao, Tzu-Chiang; Hwang, Wei |
| 國立臺灣大學 |
2004-08 |
A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 元智大學 |
2014-04-26 |
A 1.8 GHz CMOS High-Linear Power-Combining Power Amplifier Using On-Chip Transmission Line Transformer
|
Ming-Yi Chen; Jeng-Rern Yang |
| 國立中山大學 |
2009-12 |
A 1.8 V to 3.3 V Level-Converting Flip-Flop Design for Multiple Power Supply Systems
|
C.C. Wang;K.S.M. Li;S.J. Wang |
| 國立交通大學 |
2014-12-08T15:25:41Z |
A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end
|
Chen, WZ; Cheng, YL; Lin, DS |
| 臺大學術典藏 |
2021-03-12T08:40:55Z |
A 1.8-GHz Near-Field Dielectric Plethysmography Heart-Rate Sensor with Time-Based Edge Sampling
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
| 國立交通大學 |
2014-12-08T15:18:59Z |
A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end
|
Chen, WZ; Cheng, YL; Lin, DS |
| 淡江大學 |
2013-06 |
A 1.8-V 4-ppm oC Reference Current with Process and Temperature
|
Yang, Wei-Bin; Hong, Ming-Hao; Yeh, Sheng-Shuh |
| 淡江大學 |
2015/09/13 |
A 1.8-V Temperature Coefficient is 4.36-ppm/°C Bandgap Reference Current with Process Calibration
|
Yang, Wei-Bin |
| 元智大學 |
2016-06-23 |
A 1.8/2.6 GHz CMOS High Linearity Power Amplifier for LTE application
|
Chih-Huang Lin; Jeng-Rern Yang |
| 國立交通大學 |
2019-04-02T06:04:51Z |
A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS
|
Ku, Fang-Ju; Wu, Tung-Yu; Liao, Yen-Chin; Chang, Hsie-Chia; Wong, Wing Hung; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:27:18Z |
A 1.8GHz CMOS quadrature voltage-controlled oscillator (VCO) using the constant-current LC ring oscillator structure
|
Wu, CY; Kao, HS |
| 國立臺灣大學 |
2004-08 |
A 1.8V 2.5-5.2 GHz CMOS dual-input two-stage ring VCO
|
Tu, Wei-Hsuan; Yeh, Jyh-Yih; Tsai, Hung-Chieh; Wang, Chorng-Kuang |
| 國立高雄師範大學 |
2007-09 |
A 1.8V cascoded differential CMOS LNA for WCDMA receiver front-end
|
Jian-Ming Wu;Y. S. Lin;D. Y. Tsao;S. C. Li; 吳建銘 |
| 臺大學術典藏 |
2020-01-17T07:44:50Z |
A 1.9 GHz CMOS high isolation absorptive OOK modulator
|
Ling, C.-C.; Yang, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; JAU-HORNG CHEN |
| 臺大學術典藏 |
2020-11-03T09:53:14Z |
A 1.9-mW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Huang S.-A.;Chang K.-C.;Horng-Huei Liou;Yang C.-H.; Huang S.-A.; Chang K.-C.; HORNG-HUEI LIOU; Yang C.-H. |
| 臺大學術典藏 |
2021-02-26T08:42:03Z |
A 1.9-mW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Huang, S.-A.; Chang, K.-C.; Liou, H.-H.; Yang, C.-H.; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2021-02-26T08:42:04Z |
A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems
|
Wen, C.-C.; Lee, Y.-C.; Wu, Y.-C.; Kao, C.-C.; Yang, C.-H.; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2018-09-10T15:26:09Z |
A 1.96 mm 2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols
|
CR Tsai;MC Hsiao;WC Shen;AYA Wu;CM Cheng; CR Tsai; MC Hsiao; WC Shen; AYA Wu; CM Cheng; CHEN-MOU CHENG; AN-YEU(ANDY) WU |
| 國立交通大學 |
2014-12-08T15:09:28Z |
A 1.9mW portable ADPLL-based frequency synthesizer for high speed clock generation
|
Chang, Ming-Hung; Yang, Zong-Xi; Hwang, Wei |
| 臺大學術典藏 |
2020-02-26T07:30:06Z |
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Huang S.-A; Chang K.-C; HORNG-HUEI LIOU; Yang C.-H. |
| 臺大學術典藏 |
2018 |
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Yang C.-H.; HORNG-HUEI LIOU; Chang K.-C.; Huang S.-A.; Huang S.-A.;Chang K.-C.;Horng-Huei Liou;Yang C.-H. |
