| 國立暨南國際大學 |
2010 |
A 4.9-dB NF 53.5-to 62-GHz MICROMACHINED CMOS WIDEBAND LNA WITH SMALL GROUP-DELAY-VARIATION
|
陳志成?; Chen, CC |
| 國立暨南國際大學 |
2010 |
A 4.9-dB NF 53.5-to 62-GHz MICROMACHINED CMOS WIDEBAND LNA WITH SMALL GROUP-DELAY-VARIATION
|
林佑昇?; Lin, YS |
| 臺大學術典藏 |
2018-09-10T04:59:55Z |
A 4.92-5.845GHz Direct-Conversion CMOS Transceiver for IEEE 802.11a Wireless LAN
|
E. Lin; K. Carter; M. Kappes; Z.M. Shi; L. Lin; S. Wu; S. An; ; T. Nguyen; D. Yuan; Y.C. Wong; V. Fong; B. Yeung; A. Rofougaran; A. Behzad; TSUNG-HSIEN LIN et al. |
| 國立臺灣科技大學 |
2016 |
A 4.9GHz low power QVCO using injection locked techniques for wireless wearable applications
|
Lai, W.-C;Jang, S.-L;Su, Su S.-S. |
| 國立交通大學 |
2019-04-02T06:04:37Z |
A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking
|
Hung, Chia-Tse; Huang, Yu-Ping; Chen, Wei-Zen |
| 國立交通大學 |
2014-12-08T15:30:06Z |
A 40 Gbps Optical Receiver Analog Front-End in 65 nm CMOS
|
Chou, Shun-Tien; Huang, Shih-Hao; Hong, Zheng-Hao; Chen, Wei-Zen |
| 國立交通大學 |
2014-12-08T15:08:35Z |
A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18 mu m CMOS Technology
|
Tsai, Chia-Ming |
| 國立交通大學 |
2014-12-08T15:36:13Z |
A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist
|
Chiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T11:20:58Z |
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
|
Lien, Nan-Chun; Chu, Li-Wei; Chen, Chien-Hen; Yang, Hao-I.; Tu, Ming-Hsien; Kan, Paul-Sen; Hu, Yong-Jyun; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:32:53Z |
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis
|
Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia |
| 國立交通大學 |
2017-04-21T06:48:17Z |
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis
|
Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia |
| 國立成功大學 |
2007-02 |
A 40 to 9001 MHz CMOS broadband differential LNA for a DTV RF tuner
|
Chuang, Huey-Ru; Chuang, Huey-Ru; Chu, Y. K.; Lu, C. L. |
| 國立成功大學 |
2015-05 |
A 40-110 GHz High-Isolation CMOS Traveling-Wave T/R Switch by Using Parallel Inductor
|
Lai, Wen-Chian; Chuang, Huey-Ru |
| 國立臺灣大學 |
2007 |
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 臺大學術典藏 |
2018-09-10T07:08:34Z |
A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
|
Chih-Fan Liao;Shen-Iuan Liu; Chih-Fan Liao; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立交通大學 |
2014-12-08T15:21:11Z |
A 40-Gb/s OFDM PON System Based on 10-GHz EAM and 10-GHz Direct-Detection PIN
|
Chen, Hsing-Yu; Wei, Chia Chien; Hsu, Dar-Zu; Yuang, Maria C.; Chen, Jyehong; Lin, Yu-Min; Tien, Po-Lung; Lee, Steven S. W.; Lin, Shih-Hsuan; Li, Wei-Yuan; Hsu, Chih-Hung; Shih, Ju-Lin |
| 臺大學術典藏 |
2018-09-10T08:46:27Z |
A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithm
|
Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立臺灣大學 |
2004-04 |
A 40-GHz Frequency Divider in 0.18-m CMOS Technology
|
Lee, Jri; Razavi, Behzad |
| 臺大學術典藏 |
2019-10-24T07:28:01Z |
A 40-GHz high linearity transmitter in 65-nm CMOS technology with 32-dBm OIP3
|
王暉;HUEI WANG;Huei Wang;Chun-Nien Chen;Yen-Ting Lin;Tai-Yu Kuo; Tai-Yu Kuo; Yen-Ting Lin; Chun-Nien Chen; Huei Wang; HUEI WANG; 王暉 |
| 臺大學術典藏 |
2019-10-24T07:28:01Z |
A 40-GHz high linearity transmitter in 65-nm CMOS technology with 32-dBm OIP3
|
王暉;HUEI WANG;Huei Wang;Chun-Nien Chen;Yen-Ting Lin;Tai-Yu Kuo; Tai-Yu Kuo; Yen-Ting Lin; Chun-Nien Chen; Huei Wang; HUEI WANG; 王暉 |
| 國立臺灣大學 |
2009 |
A 40-GHz low-noise amplifier with a positive-feedback network in 0.18-μm CMOS
|
Hsieh, Hsieh-Hung; Lu, Liang-Hung |
| 臺大學術典藏 |
2018-09-10T07:43:05Z |
A 40-GHz low-noise amplifier with a positive-feedback network in 0.18-μm CMOS
|
H.-H. Hsieh;L.-H. Lu; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU |
| 臺大學術典藏 |
2009 |
A 40-GHz low-noise amplifier with a positive-feedback network in 0.18-μm CMOS
|
Hsieh, H.-H.;Lu, L.-H.; Hsieh, H.-H.; Lu, L.-H.; LIANG-HUNG LU |
| 臺大學術典藏 |
2021-03-12T08:41:04Z |
A 40-GHz wide-tuning-range VCO in 0.18-μm CMOS
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
