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Showing items 916741-916765 of 2348419 (93937 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:04:18Z |
VLSI IMPLEMENTATION OF AN M-ARRAY IMAGE FILTER BASED ON SHIFT REGISTER ARRAY
|
LEE, CY; TSAI, JM; HSU, SC |
| 中國文化大學 |
2018-04 |
VLSI implementation of an ultra-low-cost and low-power image compressor for wireless camera networks
|
Chen, SL (Chen, Shih-Lun); Nie, J (Nie, Jing); Lin, TL (Lin, Ting-Lan); Chung, RL (Chung, Rih-Lung); Hsia, CH (Hsia, Chih-Hsien); Liu, TY (Liu, Tse-Yen); Lin, SY (Lin, Szu-Yin); Wu, HX (Wu, Hai-Xia) |
| 中華大學 |
2006 |
VLSI Implementation of CORDIC-Based Geometry Rotation for High-Speed 3-D Computer Graphic Systems
|
宋志雲; Sung, Tze-Yun |
| 國立中山大學 |
1997-06 |
VLSI Implementation of Digit-On-Line CORDIC with Constant Scaling Factor
|
Shen-Fu Hsiao; Jen-Yin Chen |
| 中華大學 |
2008 |
VLSI Implementation of Discrete Wavelet Transform with Lifting Scheme
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Implementation of Double- Rotation CORDIC Arithmetic
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
VLSI Implementation of Double- Rotation CORDIC Arithmetic (DRCA)
|
宋志雲; Sung, Tze-Yun |
| 國立中山大學 |
1994-12 |
VLSI Implementation of Fully Pipelined Hadamard Transform
|
Shen-Fu Hsiao; Vincent Tsai |
| 中華大學 |
2006 |
VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors
|
謝曜式; Shieh, Yaw-Shih |
| 國立聯合大學 |
2007 |
VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems
|
Tze-Yun Sung, Hsi-Chin Hsin |
| 中華大學 |
2007 |
VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems
|
宋志雲; Sung, Tze-Yun |
| 國立成功大學 |
2004-06 |
VLSI implementation of implantable wireless power and data transmission micro-stimulator for neuromuscular stimulation
|
Lee, Shuenn-Yuh; Lev, Shyh-Chyang; Chen, Jia-Jin Jason |
| 中華大學 |
2013 |
VLSI IMPLEMENTATION OF LOW-POWER AND HIGH-SFDR DIGITAL FREQUENCY SYNTHESIZER FOR UNDERWATER INSTRUMENTS AND NETWORK SYSTEMS
|
莊英慎; Juang, Ying-Shen |
| 中華大學 |
2013 |
VLSI IMPLEMENTATION OF LOW-POWER AND HIGH-SFDR DIGITAL FREQUENCY SYNTHESIZER FOR UNDERWATER INSTRUMENTS AND NETWORK SYSTEMS
|
宋志雲; Sung, Tze-Yun |
| 國立高雄第一科技大學 |
2006.04 |
VLSI implementation of low-power high-quality color interpolation processor for CCD camera
|
Hsia, Shih-Chang;Chen, Ming-Huei;Tsai, Po-Shien |
| 中華大學 |
2006 |
VLSI Implementation of Memory-Efficiency Multiplierless DCT and IDCT Processors
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Implementation of Memory-Efficiency Multiplierless DCT and IDCT Processors
|
謝曜式; Shieh, Yaw-Shih |
| 國立中山大學 |
1995-12 |
VLSI implementation of multi-valued exponential bidirectional associative memory using current-mode circuits
|
C.C. Wang;Y.C. Chen |
| 中華大學 |
2005 |
VLSI Implementation of Pipelined Architectures for 2-D Discrete Wavelet Transform and Its Inversion
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2005 |
VLSI Implementation of Pipelined Architectures for 2-D Discrete Wavelet Transform and Its Inversion
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2005 |
VLSI Implementation of Pipelined Architectures for 2-D Discrete Wavelet Transform and Its Inversion
|
林國珍; Lin, Kuo-Jen |
| 臺大學術典藏 |
2018-09-10T09:48:39Z |
VLSI implementation of real-time motion compensated beamforming in synthetic transmit aperture imaging
|
Ho, K.-Y.;Chen, Y.-H.;Zhan, C.-Z.;y Wu, A.-Y.; Ho, K.-Y.; Chen, Y.-H.; Zhan, C.-Z.; y Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:07:51Z |
VLSI implementation of shape-adaptive discrete wavelet transform
|
Tseng, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T06:54:39Z |
VLSI implementation of the motion estimator with two-dimensional data-reuse
|
Lai, Y.-K.; Lai, Y.-L.; Liu, Y.-C.; Chen, L.-G.; LIANG-GEE CHEN |
Showing items 916741-916765 of 2348419 (93937 Page(s) Totally)
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