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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:42:57Z	A 0.7-V 60-GHz Low-Power LNA with Forward Body Bias Technique in 90 nm CMOS Process	Wei-Heng Lin; Jeng-Han Tsai; Yung-Nien Jen; Tian-Wei Huang; Huei Wang; TIAN-WEI HUANG; Wei-Heng Lin;Jeng-Han Tsai;Yung-Nien Jen;Tian-Wei Huang;Huei Wang
臺大學術典藏	2020-06-04T07:53:46Z	A 0.7-V 60-GHz low-power LNA with forward body bias technique in 90 nm CMOS process	Lin, W.-H.;Tsai, J.-H.;Jen, Y.-N.;Huang, T.-W.;Wang, H.; Lin, W.-H.; Tsai, J.-H.; Jen, Y.-N.; Huang, T.-W.; Wang, H.; HUEI WANG
國立高雄師範大學	2012-12	A 0.7-V Input Output-capacitor-free Digitally Controlled Low-dropout Regulator with High Current Efficiency in 0.35-?m CMOS Technology	Yu-Lung Lo;Wei-Jen Chen; 羅有龍
國立交通大學	2014-12-08T15:12:45Z	A 0.75 VCMOS low-noise amplifier for ultra wide-band wireless receiver	Wu, Hui-I.; Hsiung, Zi Hao; Jou, Christina F.
國立交通大學	2014-12-08T15:34:48Z	A 0.75-2.67 GHz 5-bit Vector-Sum Phase Shifter	Yan, Tzu-Chao; Lin, Wei-Zhen; Kuo, Chien-Nan
國立東華大學	2007-09	A 0.7V 3-5GHz CMOS Low Noise Amplifier for Ultra-wideband Applications	翁若敏; Weng, Ro-Min; Hsiao, Chih-Lung ; Lee, Wei-Chi
國立高雄師範大學	2008-06	A 0.7V Low-Voltage Folded-Cascode Uwblana with a Resistive Feedback	Ruey-Lue Wang;Cheng-Lin Huang;Shih-Chih Chen;Jui-Hao Shang;Cheng-Lung Tsai; 王瑞祿
國立臺灣大學	2006	A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop	Chang, Hsiang-Hui; Chang, Jung-Yu; Kuo, Chun-Yi; Liu, Shen-Iuan
國立臺灣大學	2004-12	A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI	Chen, H.P.; Kuo, J.B.
國立臺灣大學	2002-08	A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture	Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan

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