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Showing items 91396-91405 of 2346275 (234628 Page(s) Totally)
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| 國立臺灣大學 |
2001 |
A 2.4GHz low voltage CMOS down-conversion double-balanced mixer
|
TANG, Chih-Chun; WU, Chia-Hsin; FENG, Wu-Sheng; LIU, Shen-Iuan |
| 臺大學術典藏 |
2018-09-10T09:24:58Z |
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing
|
SHEN-IUAN LIU; Shen-Iuan Liu; Yi-Chieh Huang; Yi-Chieh Huang;Shen-Iuan Liu |
| 臺大學術典藏 |
2018-09-10T09:50:31Z |
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing
|
SHEN-IUAN LIU; Shen-Iuan Liu; Yi-Chieh Huang; Yi-Chieh Huang;Shen-Iuan Liu |
| 國立交通大學 |
2014-12-08T15:08:28Z |
A 2.5 Gbps CMOS fully integrated optical receicer with lateral PIN detector
|
Chen, Wei-Zen; Huang, Shih-Hao |
| 國立成功大學 |
2017-04 |
A 2.5 mW/ch, 50 Mcps, 10-Analog Channel, Adaptively Biased Read-Out Front-End IC With Low Intrinsic Timing Resolution for Single-Photon Time-of-Flight PET Applications With Time-Dependent Noise Analysis in 90 nm CMOS
|
Cruz;Hugo;Huang;Hong-Yi;Luo;Ching-Hsing;Lee;Shuenn-Yuh |
| 國立臺灣科技大學 |
2017 |
A 2.5-ps bin size and 6.7-ps resolution FPGA time-to-digital converter based on delay wrapping and averaging
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Chen, P;Hsiao, Y.-Y;Chung, Y.-S;Tsai, W.X;Lin, J.-M. |
| 國立交通大學 |
2014-12-08T15:05:20Z |
A 2.5-V 14-bit, 180-mW cascaded Sigma Delta ADC for ADSL2+ application
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Chang, Teng-Hung; Dung, Lan-Rong; Guo, Jwin-Yen; Yang, Kai-Jiun |
| 國立交通大學 |
2014-12-08T15:36:34Z |
A 2.56 Gb/s Soft RS (255,239) Decoder Chip for Optical Communication Systems
|
Lin, Yi-Min; Hsu, Chih-Hsiang; Chang, Hsie-Chia; Lee, Chen-Yi |
| 臺大學術典藏 |
2020-05-04T08:21:52Z |
A 2.5D Approach to 360 Panorama Video Stabilization
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Shen, L.-C.;Huang, T.-K.;Chen, C.-S.;Chuang, Y.-Y.; Shen, L.-C.; Huang, T.-K.; Chen, C.-S.; Chuang, Y.-Y.; YUNG-YU CHUANG |
| 臺大學術典藏 |
2020-05-04T08:22:04Z |
A 2.5D Approach to 360 Panorama Video Stabilization.
|
Shen, Lin-Chen; Huang, Tzu-Kuei; Chen, Chu-Song; Chuang, Yung-Yu; YUNG-YU CHUANG |
Showing items 91396-91405 of 2346275 (234628 Page(s) Totally)
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