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Showing items 92116-92125 of 2351408 (235141 Page(s) Totally)
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| 淡江大學 |
2012-07-15 |
A 400 MHz 500-fs-Jitter Open-Loop DLL-Based Multi-Phase Clock Generator Utilizing an Noise-Free All-Digital Locking Detection Circuitry
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Shih, Horng-Yuan; Chang, Yu-Chuan; Chen, Chun-Fan; Lin, Sheng-Kai |
| 臺大學術典藏 |
2018-09-10T08:19:11Z |
A 400-MHz Super-Regenerative Receiver with a Fast Digital Frequency Calibration
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H.-H. Liu;C.-J. Tung;Y.-H. Liu;T.-H. Lin; H.-H. Liu; C.-J. Tung; Y.-H. Liu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-μm CMOS
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K.-C. Liao;P.-S. Huang;W.-H. Chiu;T.-H. Lin; K.-C. Liao; P.-S. Huang; W.-H. Chiu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T09:42:58Z |
A 401GFlops/W 16-cores signal reconstruction platform with a 4G entries/s matrix generation engine for compressed sensing and sparse representation
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Tsai, Y.-M.;Yang, T.-J.;Chen, L.-G.; Tsai, Y.-M.; Yang, T.-J.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立交通大學 |
2019-04-02T06:04:27Z |
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems
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Ng, Chee-Kit; Lin, Yu-Chun; Liu, Wei-Chang; Wu, Chin-Feng; Lou, Shyh-Lye |
| 臺大學術典藏 |
2018-09-10T07:42:01Z |
A 40Gb/s decision feedback equalizer using back-gate feedback technique
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Chang-Lin Hsieh;Shen-Iuan Liu; Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T07:06:07Z |
A 40Gb/s TX and RX chip set in 65nm CMOS
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Chen, M.-S.;Shih, Y.-N.;Lin, C.-L.;Hung, H.-W.;Lee, J.; Chen, M.-S.; Shih, Y.-N.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE |
| 元智大學 |
2013-08-05 |
A 40MHZ IF BAND PASS FILTER FOR DSRC SYSTEM
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Hungwen Lin; Jin-Yi Lin; Min-Tai Chuang |
| 國立交通大學 |
2015-07-21T08:31:00Z |
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
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Liao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun |
| 國立交通大學 |
2014-12-08T15:35:45Z |
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
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Chang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang |
Showing items 92116-92125 of 2351408 (235141 Page(s) Totally)
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