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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 92061-92070 / 2348419 (共234842頁)
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每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2019-08-27T04:20:05Z |
A 49-Year-Old Man with Combined Myasthenia Gravis, Autoimmune Thyroiditis and IgG4 Orbitopathy
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Shan-Han Chang;Yung-Xin Tsai;Ta-Fu Chen;Wan-Chen Wu;Pei-Lung Chen;Jin-Ying Lu; Shan-Han Chang; Yung-Xin Tsai; TA-FU CHEN; WAN-CHEN WU; PEI-LUNG CHEN; Jin-Ying Lu |
| 國立中山大學 |
2001-08 |
A 4Kb DRAM using temperature-insensitive self-recharging circuitry
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C.C. Wang;C.C. Chiu |
| 國立交通大學 |
2014-12-08T15:36:28Z |
A 4n-move self-stabilizing algorithm for the minimal dominating set problem using an unfair distributed daemon
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Chiu, Well Y.; Chen, Chiuyuan; Tsai, Shih-Yu |
| 臺大學術典藏 |
2018-09-10T08:15:08Z |
A 4–17 GHz Darlington Cascode Broadband Medium Power Amplifier in 0.18-$\\mu$ m CMOS Technology
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Pin-Cheng Huang;Kun-You Lin;Huei Wang; Pin-Cheng Huang; Kun-You Lin; Huei Wang; HUEI WANG; KUN-YOU LIN |
| 國立臺灣大學 |
2010 |
A 4–17 GHz darlington cascode broadband medium power amplifier in 0.18-μm CMOS technology
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Huang, Pin-Cheng; Lin, Kun-You; Wang, Huei |
| 國立臺灣大學 |
2007 |
A 4–41 GHz Singly Balanced Distributed Mixer Using GaAs pHEMT Technology
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Chang, F.-C.; Wu, P.-S.; Lei, M.-F.; Wang, H. |
| 淡江大學 |
2024-10-25 |
A 5 Gb/s Receiver with Decision Feedback Equalizer and Baud-Rate Clock and Data Recovery Circuit for 8K Displays in 90 nm CMOS Process
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Lin, Wei-Ting;Lin, Hung-Yen;Shih, Horng-Yuan |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis
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Su, W.-J.;Liu, S.-I.; Su, W.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 國立成功大學 |
2004-02 |
A 5 GHz 0.18 mu m CMOS mixer for 802.11a WLAN receiver applications
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Chu, Yuan-Kai; Chuang, Huey-Ru |
| 臺大學術典藏 |
2018-09-10T07:42:49Z |
A 5 GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched-capacitors
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P.-Y. Deng;J.-F. Kiang; P.-Y. Deng; J.-F. Kiang; JEAN-FU KIANG |
顯示項目 92061-92070 / 2348419 (共234842頁)
<< < 9202 9203 9204 9205 9206 9207 9208 9209 9210 9211 > >>
每頁顯示[10|25|50]項目
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