| 臺大學術典藏 |
2021-03-12T08:41:04Z |
A 40-GHz wide-tuning-range VCO in 0.18-μm CMOS
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
| 臺大學術典藏 |
2020-01-17T07:44:47Z |
A 40-MHz Bandwidth Pulse-Modulated Polar Transmitter for Mobile Applications
|
Chen, Y.-H.; Wang, T.-H.; Lin, S.-C.; Chen, J.-H.; Chen, Y.-J.E.; JAU-HORNG CHEN; JAU-HORNG CHEN;Chen, Y.-J.E.;Chen, J.-H.;Lin, S.-C.;Wang, T.-H.;Chen, Y.-H. |
| 臺大學術典藏 |
2020-06-11T06:47:58Z |
A 40-MHz Bandwidth Pulse-Modulated Polar Transmitter for Mobile Applications
|
Chen, Y.-H.;Wang, T.-H.;Lin, S.-C.;Chen, J.-H.;Chen, Y.-J.E.; Chen, Y.-H.; Wang, T.-H.; Lin, S.-C.; Chen, J.-H.; Chen, Y.-J.E.; YI-JAN EMERY CHEN |
| 國立交通大學 |
2014-12-08T15:12:37Z |
A 40-MHz double differential-pair CMOS OTA with-60-dB IM3
|
Lo, Tien-Yu; Hung, Chung-Chih |
| 國立臺灣大學 |
2011 |
A 40-mm High-Temperature Superconducting Surface Resonator in a 3-T MRI System: Simulations and Measurements
|
Lin, In-Tsang; Yang, Hong-Chang; Chen, Jyh-Horng |
| 臺大學術典藏 |
2020-06-11T06:47:20Z |
A 40-mm high-temperature superconducting surface resonator in a 3-T MRI system: Simulations and measurements
|
Lin, I.-T.;Yang, H.-C.;Chen, J.-H.Jyh-Horng Chen; Lin, I.-T.; Yang, H.-C.; Chen, J.-H.; JYH-HORNG CHEN |
| 臺大學術典藏 |
2021-09-02T00:05:07Z |
A 40-nm CMOS mixer with 36-GHz if bandwidth and 60-148 GHz RF passband
|
Wu Y.-C;Hwang Y.-J;Chiong C.-C;Lu B.-Z;Wang H.; Wu Y.-C; Hwang Y.-J; Chiong C.-C; Lu B.-Z; Wang H.; HUEI WANG |
| 臺大學術典藏 |
2019-10-24T08:40:01Z |
A 40-nm CMOS V-band single-pole quadruple-throw absorptive switch for phased-array applications
|
KUN-YOU LIN;Kun-You Lin;Kao-Yao Kao;Dong-Ru Lin; Dong-Ru Lin; Kao-Yao Kao; Kun-You Lin; KUN-YOU LIN |
| 國立交通大學 |
2014-12-08T15:25:10Z |
A 40-nm-Gate InAs/In(0.7)Ga(0.3)As Composite-Channel HEMT with 2200 mS/mm and 500-GHz f(T)
|
Kuo, Chien-I; Hsu, Heng-Tung; Wu, Chien-Ying; Chang, Edward Yi; Miyamoto, Yasuyuki; Chen, Yu-Lin; Biswas, Dhrubes |
| 元智大學 |
2009-05 |
A 40-nm-Gate InAs/InGaAs Composite-Channel HEMT with 2200 mS/mm and 500-GHz fT
|
許恒通; Chien-I Kuo; Chien-Ying Wu; Edward Yi Chang; Yasuyuki Miyamoto; Yu-Lin Chen; Dhrubes Biswas |
| 元智大學 |
2009-05 |
A 40-nm-Gate InAs/InGaAs Composite-Channel HEMT with 2200 mS/mm and 500-GHz fT
|
許恒通; Chien-I Kuo; Chien-Ying Wu; Edward Yi Chang; Yasuyuki Miyamoto; Yu-Lin Chen; Dhrubes Biswas |
| 臺大學術典藏 |
2020-06-11T06:16:47Z |
A 40.4-dB Range, 0.73-dB Step, and 0.07-dB Error Programmable Gain Amplifier Using Gain Error Shifting Technique
|
Wang, L.-S.;Ku, P.-C.;Ko, P.-T.;Chung, C.-J.;Lu, L.-H.; Wang, L.-S.; Ku, P.-C.; Ko, P.-T.; Chung, C.-J.; Lu, L.-H.; LIANG-HUNG LU |
| 國立成功大學 |
2019 |
A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth
|
Hung, T.-C.;Kuo, T.-H. |
| 淡江大學 |
2010-12-12 |
A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process
|
施鴻源; 陳秋榜 |
| 淡江大學 |
2012-07-15 |
A 400 MHz 500-fs-Jitter Open-Loop DLL-Based Multi-Phase Clock Generator Utilizing an Noise-Free All-Digital Locking Detection Circuitry
|
Shih, Horng-Yuan; Chang, Yu-Chuan; Chen, Chun-Fan; Lin, Sheng-Kai |
| 臺大學術典藏 |
2018-09-10T08:19:11Z |
A 400-MHz Super-Regenerative Receiver with a Fast Digital Frequency Calibration
|
H.-H. Liu;C.-J. Tung;Y.-H. Liu;T.-H. Lin; H.-H. Liu; C.-J. Tung; Y.-H. Liu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-μm CMOS
|
K.-C. Liao;P.-S. Huang;W.-H. Chiu;T.-H. Lin; K.-C. Liao; P.-S. Huang; W.-H. Chiu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T09:42:58Z |
A 401GFlops/W 16-cores signal reconstruction platform with a 4G entries/s matrix generation engine for compressed sensing and sparse representation
|
Tsai, Y.-M.;Yang, T.-J.;Chen, L.-G.; Tsai, Y.-M.; Yang, T.-J.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立交通大學 |
2019-04-02T06:04:27Z |
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems
|
Ng, Chee-Kit; Lin, Yu-Chun; Liu, Wei-Chang; Wu, Chin-Feng; Lou, Shyh-Lye |
| 臺大學術典藏 |
2018-09-10T07:42:01Z |
A 40Gb/s decision feedback equalizer using back-gate feedback technique
|
Chang-Lin Hsieh;Shen-Iuan Liu; Chang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T07:06:07Z |
A 40Gb/s TX and RX chip set in 65nm CMOS
|
Chen, M.-S.;Shih, Y.-N.;Lin, C.-L.;Hung, H.-W.;Lee, J.; Chen, M.-S.; Shih, Y.-N.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE |
| 元智大學 |
2013-08-05 |
A 40MHZ IF BAND PASS FILTER FOR DSRC SYSTEM
|
Hungwen Lin; Jin-Yi Lin; Min-Tai Chuang |
| 國立交通大學 |
2015-07-21T08:31:00Z |
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
|
Liao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun |
| 國立交通大學 |
2014-12-08T15:35:45Z |
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
|
Chang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang |
| 國立交通大學 |
2018-08-21T05:54:34Z |
A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications
|
Tsai, Chang-Hung; Yu, Wan-Ju; Wong, Wing Hung; Lee, Chen-Yi |
