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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 91981-91990 / 2348419 (共234842頁)
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| 國立交通大學 |
2014-12-08T15:32:53Z |
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis
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Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia |
| 國立成功大學 |
2007-02 |
A 40 to 9001 MHz CMOS broadband differential LNA for a DTV RF tuner
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Chuang, Huey-Ru; Chuang, Huey-Ru; Chu, Y. K.; Lu, C. L. |
| 國立成功大學 |
2015-05 |
A 40-110 GHz High-Isolation CMOS Traveling-Wave T/R Switch by Using Parallel Inductor
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Lai, Wen-Chian; Chuang, Huey-Ru |
| 國立臺灣大學 |
2007 |
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
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Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
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Liao, Chih-Fan; Liu, Shen-Iuan |
| 臺大學術典藏 |
2018-09-10T07:08:34Z |
A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
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Chih-Fan Liao;Shen-Iuan Liu; Chih-Fan Liao; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立交通大學 |
2014-12-08T15:21:11Z |
A 40-Gb/s OFDM PON System Based on 10-GHz EAM and 10-GHz Direct-Detection PIN
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Chen, Hsing-Yu; Wei, Chia Chien; Hsu, Dar-Zu; Yuang, Maria C.; Chen, Jyehong; Lin, Yu-Min; Tien, Po-Lung; Lee, Steven S. W.; Lin, Shih-Hsuan; Li, Wei-Yuan; Hsu, Chih-Hung; Shih, Ju-Lin |
| 臺大學術典藏 |
2018-09-10T08:46:27Z |
A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithm
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Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立臺灣大學 |
2004-04 |
A 40-GHz Frequency Divider in 0.18-m CMOS Technology
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Lee, Jri; Razavi, Behzad |
| 臺大學術典藏 |
2019-10-24T07:28:01Z |
A 40-GHz high linearity transmitter in 65-nm CMOS technology with 32-dBm OIP3
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王暉;HUEI WANG;Huei Wang;Chun-Nien Chen;Yen-Ting Lin;Tai-Yu Kuo; Tai-Yu Kuo; Yen-Ting Lin; Chun-Nien Chen; Huei Wang; HUEI WANG; 王暉 |
顯示項目 91981-91990 / 2348419 (共234842頁)
<< < 9194 9195 9196 9197 9198 9199 9200 9201 9202 9203 > >>
每頁顯示[10|25|50]項目
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