English  |  正體中文  |  简体中文  |  總筆數 :2830302  
造訪人次 :  32493517    線上人數 :  605
教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
關於TAIR

瀏覽

消息

著作權

相關連結

跳至: [ 中文 ] [ 數字0-9 ] [ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z ]
請輸入前幾個字:   

顯示項目 90101-90125 / 2314381 (共92576頁)
<< < 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 > >>
每頁顯示[10|25|50]項目

機構 日期 題名 作者
國立臺灣科技大學 2009 A (t, n)-fair dynamic threshold secret sharing scheme Lin T.-Y.; Wu T.-C.; Lee C.-I.; Wu T.-S.
國立臺灣海洋大學 2009 A (t, n)-fair dynamic threshold secret sharing scheme T.-Y. Lin;T.-C. Wu;C.-I. Lee;T.-S. Wu
國立臺灣海洋大學 2009 A (t, n)-fair dynamic threshold secret sharing scheme Tzong-Sun Wu;Han-Yu Lin;Chien-Lung Hsu;Kuo-Yi Chang
亞洲大學 2004-04 A (t,n) Multi-secret Sharing Scheme 黃明祥;Hwang, Min-Shiang
亞洲大學 2005-09 A (t,n) Threshold Secret Sharing System with Efficient Identification of Cheaters Lin, I. C. ; Chang, C. C
國立臺灣大學 2009-10-12 A + B model in Quantum Geometry Wang, Chin-Lung
國立臺灣大學 2015 A + B theory in conifold transitions for Calabi-Yau threefolds Lin, Hui-Wen; Lee, Y.-P.; Wang, C.-L.
臺大學術典藏 2015 A + B theory in conifold transitions of Calabi--Yau threefolds Wang, Chin-Lung;Lee, Y.-P.;Lin, H.-W.; Wang, Chin-Lung; Lee, Y.-P.; Lin, H.-W.
國立臺灣大學 2015 A + B theory in conifold transitions of Calabi--Yau threefolds Wang, Chin-Lung; Lee, Y.-P.; Lin, H.-W.
國立交通大學 2014-12-08T15:38:30Z A +/- 6ms-Accuracy, 0.68mm(2) and 2.21 mu W QRS Detection ASIC Wang, Hui-Min; Lai, You-Liang; Hou, Mark C.; Lin, Shih-Hsiang; Yen, Brad S.; Huang, Yu-Chieh; Chou, Lei-Chun; Hsu, Shao-You; Huang, Sheng-Chieh; Jan, Ming-Yie
臺大學術典藏 2020-06-11T06:46:01Z A -194 dBc/Hz FOM interactive current-reused QVCO (ICR-QVCO) with capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique Wu, K.-I.;Shen, I.-S.;Jou, C.F.;Chen, C.C.-P.; Wu, K.-I.; Shen, I.-S.; Jou, C.F.; Chen, C.C.-P.; CHUNG-PING CHEN
國立臺灣科技大學 2014 A -21.2 -dBm dual-channel UHF passive CMOS RFID tag design Yao, C.-Y.;Hsia, W.-C.
國立臺灣大學 2006 A -expectation tolerance interval for general balanced mixed linear models Lin, Tsai-Yu; Liao, Chen-Tuo
臺大學術典藏 2013 A 0.004mm2 single-channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS Tai, H.-Y.;Tsai, P.-Y.;Tsai, C.-H.;Chen, H.-S.; Tai, H.-Y.; Tsai, P.-Y.; Tsai, C.-H.; Chen, H.-S.; HSIN-SHU CHEN
國立臺灣大學 2010 A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology Huang, Yen-Chuan; Lee, Tai-Cheng
臺大學術典藏 2018-09-10T08:19:08Z A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
國立交通大學 2014-12-08T15:34:51Z A 0.0354mm(2) 82 mu W 125KS/s 3-Axis Readout Circuit for Capacitive MEMS Accelerometer Lai, Kelvin Yi-Tse; He, Zih-Cheng; Yang, Yu-Tao; Chang, Hsie-Chia; Lee, Chen-Yi
國立交通大學 2019-08-02T02:18:26Z A 0.05 V driven ammonia gas sensor based on an organic diode with a top porous layered electrode and an air-stable sensing film Madhaiyan, Govindasamy; Chen, Chao-Hsuan; Wu, Yi-Chu; Horng, Sheng-Fu; Zan, Hsiao-Wen; Meng, Hsin-Fei; Lin, Hong-Cheu
國立成功大學 2020- A 0.07-mm(2) 162-mW DAC Achieving >65 dBc SFDR and <-70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing Huang;Hung-Yi;Kuo;Tai-Haur
國立成功大學 2020 A 0.07-mm2162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s with Output Impedance Compensation and Concentric Parallelogram Routing Huang, Huang H.-Y.;Kuo, T.-H.
臺大學術典藏 2018-09-10T08:08:01Z A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine Cheng, C.-C.; Tsai, Y.-M.; Chen, L.-G.; Ch; rakasan, A.P.; LIANG-GEE CHEN; Cheng, C.-C.;Tsai, Y.-M.;Chen, L.-G.;Ch;rakasan, A.P.
國立成功大學 2019 A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation Huang, Huang H.-Y.;Kuo, T.-H.
國立交通大學 2014-12-08T15:29:01Z A 0.09 mu W Low Power Front-End Biopotential Amplifier for Biosignal Recording Tseng, Yuhwai; Ho, Yingchieh; Kao, Shuoting; Su, Chauchin
國立交通大學 2014-12-08T15:22:37Z A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters Ho, Yingchieh; Su, Chauchin
國立臺灣大學 2004-06 A 0.1-23-GHz SiGe BiCMOS analog multiplier and mixer based on attenuation-compensation technique Tsai, Ming-Da; Lin, Chin-Shen; Wang, Chi-Hsueh; Lien, Chun-Hsien; Wang, Huei

顯示項目 90101-90125 / 2314381 (共92576頁)
<< < 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 > >>
每頁顯示[10|25|50]項目