| 淡江大學 |
2001-09 |
A 1.2 V 500 MHz 32-bit carry-lookahead adder
|
鄭國興; Cheng, Kuo-hsing; Lee, Wen-shiuan; Huang, Yung-chong |
| 國立交通大學 |
2014-12-08T15:27:23Z |
A 1.2 V CMOS four-quadrant analog multiplier
|
Hsiao, SY; Wu, CY |
| 淡江大學 |
1996-10-13 |
A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic
|
鄭國興; Cheng, Kuo-hsing; Yee, Liow yu |
| 淡江大學 |
1997-12-15 |
A 1.2 V low-power TSPC complementary pass transistor logic
|
鄭國興; Cheng, Kuo-hsing; Chen, Jian-hung |
| 國立成功大學 |
2002-09 |
A 1.2 V rail-to-rail analog CMOS rank-order filter with k-WTA capability
|
Hung, Yu-Cherng; Liu, Bin-Da |
| 國立臺灣大學 |
2007 |
A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology
|
Cho, Lan-Chou; Lee, Chihun; Liu, Shen-Iuan |
| 國立交通大學 |
2014-12-08T15:28:31Z |
A 1.2-V 5.2-mW 20-30-GHz Wideband Receiver Front-End in 0.18-mu m CMOS
|
Li, Chun-Hsing; Kuo, Chien-Nan; Kuo, Ming-Ching |
| 臺大學術典藏 |
2020-08-05T02:45:27Z |
A 1.2-V 5.2-mW 20-30-GHz wideband receiver front-end in 0.18-μm CMOS
|
Chun-Hsing Li; Chien-Nan Kuo; and Ming-Ching Kuo; CHUN-HSING LI; CHUN-HSING LI |
| 臺大學術典藏 |
2018-09-10T14:53:48Z |
A 1.2-V 90-nm fully integrated compact CMOS linear power amplifier using the coupled l-shape concentric vortical transformer
|
Yang, H.-S.;Chen, J.-H.;Chen, Y.-J.E.; Yang, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; YI-JAN EMERY CHEN |
| 臺大學術典藏 |
2020-01-17T07:44:51Z |
A 1.2-V 90-nm fully integrated compact CMOS linear power amplifier using the coupled l-shape concentric vortical transformer
|
Yang, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; JAU-HORNG CHEN |
| 國立交通大學 |
2014-12-08T15:41:23Z |
A 1.2-V fully integrated 2.4-GHz low-noise amplifier in 0.35-mu m CMOS technology
|
Meng, CC; Chiang, MH; Wu, TH |
| 國立交通大學 |
2014-12-08T15:44:44Z |
A 1.2-V operation power pseudomorphic high electron mobility transistor for personal handy phone handset application
|
Chang, EY; Lee, DH; Chen, SH |
| 南台科技大學 |
2001-05 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder
|
Chua-Chin Wang; Po-Ming Lee; Rong-Chin Lee; Chenn-Jung Huang; 王朝欽;李博明 |
| 南台科技大學 |
2001-05 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder
|
Chua-ChinWang; Po-Ming Lee; Rong-Chin Lee |
| 國立中山大學 |
2001-05 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder
|
C.C. Wang;P.M. Lee;R.C. Lee;C.T. Huang |
| 南台科技大學 |
2003-09 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
Chua-Chin Wang; Yih-Long Tseng; 李博明; Po-Ming Lee; Rong-Chin Lee; Chenn-Jung Hunng; 王朝欽 |
| 南台科技大學 |
2003-09 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
Chua-Chin Wang; Yih-Long Tseng; Po-Ming Lee; Rong-Chin Lee; Chenn-Jung Huang |
| 國立中山大學 |
2003 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
C.C. Wang;Y.L. Tseng;P.M. Lee;R.C. Lee;C.J. Huang |
| 國立中山大學 |
2003-09 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
C.C. Wang; Y.L. Tseng; P.M. Lee; R.C. Lee; C.J. Huang |
| 南台科技大學 |
2000-12 |
A 1.25 GHz 8-bit Tree-Structured Carry Lookahead Adder
|
Chua-Chin Wang; Po-Ming Lee; Chenn-Jung Huang; Rong-Chin Lee |
| 國立中山大學 |
2000-12 |
A 1.25 GHz 8-bit tree-structured carry lookahead adder
|
C.C. Wang;P.M. Lee;C.J. Huang;R.C. Lee |
| 國立臺灣科技大學 |
2008 |
A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition
|
Oulee C.-S.; Yang R.-J. |
| 臺大學術典藏 |
2018-09-10T08:18:16Z |
A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression
|
Chao-Ching Hung;I-Fong Chen;Shen-Iuan Liu; Chao-Ching Hung; I-Fong Chen; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立中山大學 |
2003-08 |
A 1.26ns access time current-mode sense amplifier design for SRAMs
|
C.C. Wang;Y.L. Tseng;C.C. Li;R. Hu |
| 元智大學 |
2015-08-04 |
A 1.2V 3.5Gbps Digitalized LVDS driver in 0.18um CMOS technology
|
Jhih-Siang Shao; Shi-Fung Zhou; Hungwen Lin |
