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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 91021-91030 / 2351377 (共235138頁)
<< < 9098 9099 9100 9101 9102 9103 9104 9105 9106 9107 > >>
每頁顯示[10|25|50]項目
| 國立成功大學 |
2009-02 |
A 10-40 GHZ, Broadband Subharmonic Monolithic Mixer in 0.18 mu m CMOS Technology
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Lin, Chih-Ming; Lin, Hua-Kuei; Lai, Yu-Ann; Chang, Chieh-Pin; Wang, Yeong-Her |
| 國立交通大學 |
2014-12-08T15:03:43Z |
A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCES
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CHIN, SY; WU, CY |
| 臺大學術典藏 |
2018-09-10T09:21:52Z |
A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC
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Tseng, C.-J.;Chen, H.-W.;Shen, W.-T.;Cheng, W.-C.;Chen, H.-S.; Tseng, C.-J.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.; HSIN-SHU CHEN |
| 國立暨南國際大學 |
2013 |
A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs
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蕭敬民; Hsiao, CM |
| 國立暨南國際大學 |
2013 |
A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs
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尹邦嚴; Yin, PY |
| 國立成功大學 |
2019 |
A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC
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Hu, Hu H.-J.;Cheng, Y.-S.;Chang, S.-J. |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques
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Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE |
| 國立臺灣科技大學 |
2017 |
A 10-bit 100-MS/s 2b/cycle-Assisted SAR ADC in 180nm CMOS
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Chung, Y.-H.;Tseng, H.-W. |
| 國立臺灣科技大學 |
2017 |
A 10-bit 100-MS/s SAR ADC with capacitor swapping technique in 90-nm CMOS
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Chung, Y.-H.;Shih, Shih S.-Y. |
| 國立臺灣科技大學 |
2014 |
A 10-bit 100MS/s successive approximation register analog-to-digital converter design
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Huangy, J.-F.;Laiya, W.-C.;Hsiehy, C.-G. |
顯示項目 91021-91030 / 2351377 (共235138頁)
<< < 9098 9099 9100 9101 9102 9103 9104 9105 9106 9107 > >>
每頁顯示[10|25|50]項目
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