| 國立交通大學 |
2014-12-08T15:12:44Z |
A 0.7 V transformer-feedback CMOS low-noise amplifier for 5-GHz wireless LAN
|
Wu, H. I.; Fan, R. S.; Jou, C. F. |
| 臺大學術典藏 |
2018-09-10T07:42:57Z |
A 0.7-V 60-GHz Low-Power LNA with Forward Body Bias Technique in 90 nm CMOS Process
|
Wei-Heng Lin; Jeng-Han Tsai; Yung-Nien Jen; Tian-Wei Huang; Huei Wang; TIAN-WEI HUANG; Wei-Heng Lin;Jeng-Han Tsai;Yung-Nien Jen;Tian-Wei Huang;Huei Wang |
| 臺大學術典藏 |
2020-06-04T07:53:46Z |
A 0.7-V 60-GHz low-power LNA with forward body bias technique in 90 nm CMOS process
|
Lin, W.-H.;Tsai, J.-H.;Jen, Y.-N.;Huang, T.-W.;Wang, H.; Lin, W.-H.; Tsai, J.-H.; Jen, Y.-N.; Huang, T.-W.; Wang, H.; HUEI WANG |
| 國立高雄師範大學 |
2012-12 |
A 0.7-V Input Output-capacitor-free Digitally Controlled Low-dropout Regulator with High Current Efficiency in 0.35-?m CMOS Technology
|
Yu-Lung Lo;Wei-Jen Chen; 羅有龍 |
| 國立交通大學 |
2014-12-08T15:12:45Z |
A 0.75 VCMOS low-noise amplifier for ultra wide-band wireless receiver
|
Wu, Hui-I.; Hsiung, Zi Hao; Jou, Christina F. |
| 國立交通大學 |
2014-12-08T15:34:48Z |
A 0.75-2.67 GHz 5-bit Vector-Sum Phase Shifter
|
Yan, Tzu-Chao; Lin, Wei-Zhen; Kuo, Chien-Nan |
| 國立東華大學 |
2007-09 |
A 0.7V 3-5GHz CMOS Low Noise Amplifier for Ultra-wideband Applications
|
翁若敏; Weng, Ro-Min; Hsiao, Chih-Lung ; Lee, Wei-Chi |
| 國立高雄師範大學 |
2008-06 |
A 0.7V Low-Voltage Folded-Cascode Uwblana with a Resistive Feedback
|
Ruey-Lue Wang;Cheng-Lin Huang;Shih-Chih Chen;Jui-Hao Shang;Cheng-Lung Tsai; 王瑞祿 |
| 國立臺灣大學 |
2006 |
A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop
|
Chang, Hsiang-Hui; Chang, Jung-Yu; Kuo, Chun-Yi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-12 |
A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI
|
Chen, H.P.; Kuo, J.B. |
| 臺大學術典藏 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
|
Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
|
Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 臺大學術典藏 |
2004-09 |
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator
|
Liu, Tsung-Te; Wang, Chorng-Kuang; Liu, Tsung-Te; Wang, Chorng-Kuang |
| 國立臺灣大學 |
2004-09 |
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator
|
Liu, Tsung-Te; Wang, Chorng-Kuang |
| 國立成功大學 |
2022-10 |
A 0.8-mu W and 74-dB High-Pass Sigma-Delta Modulator With OPAMP Sharing and Noise-Coupling Techniques for Biomedical Signal Acquisition
|
Lee;Shuenn-Yuh;Lee;Hao-Yun;Kung;Chia-Ho;Su;Po-Han;Chen;Ju-Yi |
| 國立臺灣大學 |
2008 |
A 0.8-mW 55-GHz dual-injection-locked CMOS frequency divider
|
Luo, Tang-Nian; Chen, Yi-Jan Emery |
| 臺大學術典藏 |
2018-09-10T06:37:55Z |
A 0.8-V 0.25-mW Current-Mirror OTA with 160-MHz GBW in 0.18-um CMOS
|
T.-H. Lin; C.-K. Wu; M.-C. Tsai; TSUNG-HSIEN LIN |
| 國立臺灣大學 |
2007 |
A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS
|
Lin, Tsung-Hsien; Wu, Chin-Kung; Tsai, Ming-Chung |
| 臺大學術典藏 |
2018-09-10T06:03:19Z |
A 0.8-V 0.25-mW Current-Mirror OTA with 160-MHz GBW in 0.18-μm CMOS
|
C.-K. Wu; M.-C. Tsai; T.-H. Lin; TSUNG-HSIEN LIN |
| 國立臺灣大學 |
2002 |
A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme
|
Lin, Perng-Fei; Kuo, J.B. |
| 臺大學術典藏 |
2018-09-10T04:15:05Z |
A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme
|
P. F. Lin; J. B. Kuo; JAMES-B KUO |
| 國立成功大學 |
2008-09 |
A 0.8-V 250-MSample/s double-sampled inverse-flip-around sample-and-hold circuit based on switched-opamp architecture
|
Ou, Hsin-Hung; Liu, Bin-Da; Chang, Soon-Jyh |
| 國立成功大學 |
2022 |
A 0.8-μW and 74-dB High-Pass Sigma-Delta Modulator with OPAMP Sharing and Noise-Coupling Techniques for Biomedical Signal Acquisition
|
Lee, S.-Y.;Lee, H.-Y.;Kung, C.-H.;Su, P.-H.;Chen, J.-Y. |
| 國立成功大學 |
2022 |
A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend
|
Wang, J.-C.;Kuo, T.-H. |
| 國立交通大學 |
2014-12-08T15:25:24Z |
A 0.8V 5.9GHz wide tuning range cmos VCO using inversion-mode bandswitching varactors
|
Wu, CY; Yu, CY |
