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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 90886-90895 / 2346288 (共234629頁)
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| 國立臺灣大學 |
2004-08 |
A 1.8V 2.5-5.2 GHz CMOS dual-input two-stage ring VCO
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Tu, Wei-Hsuan; Yeh, Jyh-Yih; Tsai, Hung-Chieh; Wang, Chorng-Kuang |
| 國立高雄師範大學 |
2007-09 |
A 1.8V cascoded differential CMOS LNA for WCDMA receiver front-end
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Jian-Ming Wu;Y. S. Lin;D. Y. Tsao;S. C. Li; 吳建銘 |
| 臺大學術典藏 |
2020-01-17T07:44:50Z |
A 1.9 GHz CMOS high isolation absorptive OOK modulator
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Ling, C.-C.; Yang, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; JAU-HORNG CHEN |
| 臺大學術典藏 |
2020-11-03T09:53:14Z |
A 1.9-mW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
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Huang S.-A.;Chang K.-C.;Horng-Huei Liou;Yang C.-H.; Huang S.-A.; Chang K.-C.; HORNG-HUEI LIOU; Yang C.-H. |
| 臺大學術典藏 |
2021-02-26T08:42:03Z |
A 1.9-mW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
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Huang, S.-A.; Chang, K.-C.; Liou, H.-H.; Yang, C.-H.; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2021-02-26T08:42:04Z |
A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems
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Wen, C.-C.; Lee, Y.-C.; Wu, Y.-C.; Kao, C.-C.; Yang, C.-H.; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2018-09-10T15:26:09Z |
A 1.96 mm 2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols
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CR Tsai;MC Hsiao;WC Shen;AYA Wu;CM Cheng; CR Tsai; MC Hsiao; WC Shen; AYA Wu; CM Cheng; CHEN-MOU CHENG; AN-YEU(ANDY) WU |
| 國立交通大學 |
2014-12-08T15:09:28Z |
A 1.9mW portable ADPLL-based frequency synthesizer for high speed clock generation
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Chang, Ming-Hung; Yang, Zong-Xi; Hwang, Wei |
| 臺大學術典藏 |
2020-02-26T07:30:06Z |
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
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Huang S.-A; Chang K.-C; HORNG-HUEI LIOU; Yang C.-H. |
| 臺大學術典藏 |
2018 |
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
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Yang C.-H.; HORNG-HUEI LIOU; Chang K.-C.; Huang S.-A.; Huang S.-A.;Chang K.-C.;Horng-Huei Liou;Yang C.-H. |
顯示項目 90886-90895 / 2346288 (共234629頁)
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每頁顯示[10|25|50]項目
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