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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 92266-92275 / 2348439 (共234844頁)
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每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2018-09-10T14:57:27Z |
A 6-Bit 1 GS/s pipeline ADC using incomplete settling with background sampling-point calibration
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Lai, C.-F.; Chen, H.-S.; HSIN-SHU CHEN; Tseng, C.-J.;Lai, C.-F.;Chen, H.-S.; Tseng, C.-J. |
| 臺大學術典藏 |
2018-09-10T14:57:27Z |
A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS
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Tai, H.-Y.;Tsai, C.-H.;Tsai, P.-Y.;Chen, H.-W.;Chen, H.-S.; Tai, H.-Y.; Tsai, C.-H.; Tsai, P.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN |
| 國立臺灣科技大學 |
2018 |
A 6-bit 1.3-GS/s ping-pong domino-SAR ADC in 55-nm CMOS
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Chung Y.-H.; Rih W.-S.; Chang C.-W. |
| 國立臺灣科技大學 |
2018 |
A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS
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Chung, Y.-H.;Rih, W.-S. |
| 臺大學術典藏 |
2004-08 |
A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter
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Chen, Yu-Hsun; Lee, Tai-Cheng; Chen, Yu-Hsun; Lee, Tai-Cheng |
| 國立臺灣大學 |
2004-08 |
A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter
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Chen, Yu-Hsun; Lee, Tai-Cheng |
| 國立臺灣大學 |
2007 |
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers
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Shen, Ding-Lan; Lee, Tai-Cheng |
| 國立成功大學 |
2012-11 |
A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications
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Chen, Ren-Li; Chang, Soon-Jyh |
| 臺大學術典藏 |
2018-09-10T07:09:32Z |
A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification
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Feng-Chiu Hsieh;Tai-Cheng; Feng-Chiu Hsieh; Tai-Cheng; TAI-CHENG LEE |
| 國立中山大學 |
2005-08 |
A 6-bit SAR pipelined ADC using improved TIQ technology
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Yan-Huei Lee;Jyi-Tsong Lin |
顯示項目 92266-92275 / 2348439 (共234844頁)
<< < 9222 9223 9224 9225 9226 9227 9228 9229 9230 9231 > >>
每頁顯示[10|25|50]項目
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