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Institution	Date	Title	Author
國立臺灣大學	2008	Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies	Chang, Chen-Haur; Lee, Chuan-Yiu; Chien, Shao-Yi
臺大學術典藏	2018-09-10T07:03:44Z	Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies	Chang, Chen-Haur; Lee, Chuan-Yiu; Chien, Shao-Yi; SHAO-YI CHIEN
臺大學術典藏	2004-05	Hardware architecture design for H.264/AVC intra frame coder	Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee; Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee
國立臺灣大學	2004-05	Hardware architecture design for H.264/AVC intra frame coder	Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee
臺大學術典藏	2018-09-10T04:47:21Z	Hardware architecture design for H.264/AVC intra frame coder	Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN
臺大學術典藏	2003-05	Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264	Hsieh, Bing-Yu; Chen, Liang-Gee; Wang, Tu-Chih; Huang, Yu-Wen; Wang, Tu-Chih; Hsieh, Bing-Yu; Chen, Liang-Gee; Huang, Yu-Wen
國立臺灣大學	2003-05	Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264	Huang, Yu-Wen; Wang, Tu-Chih; Hsieh, Bing-Yu; Chen, Liang-Gee
臺大學術典藏	2018-09-10T04:27:46Z	Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264	Huang, Y.-W.; Wang, T.-C.; Hsieh, B.-Y.; Chen, L.-G.; LIANG-GEE CHEN
國立臺灣大學	2004-08	Hardware architecture design for visual processing: present and future	Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2018-09-10T04:47:20Z	Hardware architecture design for visual processing: Present and future	Tseng, P.-C.; Chen, L.-G.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN

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