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Showing items 461081-461105 of 2348419  (93937 Page(s) Totally)
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Institution Date Title Author
國立臺灣大學 2005-08 Hardware architecture design of video compression for multimedia communication systems Chien, Shao-Yi; Huang, Yu-Wen; Chen, Ching-Yeh; Chen, Homer H.; Chen, Liang-Gee
臺大學術典藏 2018-09-10T05:15:48Z Hardware architecture design of video compression for multimedia communication systems Chen, Liang-Gee; Chen, Homer H.; Chen, Ching-Yeh; Huang, Yu-Wen; LIANG-GEE CHEN; Chien, Shao-Yi; Chien, Shao-Yi; LIANG-GEE CHEN
臺大學術典藏 2007-04-19T04:02:59Z Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile Chen, Liang-Gee;Chien, Shao-Yi;Huang, Yu-Wen;Chen, Ching-Yeh;Chao, Wei-Min; Chen, Ching-Yeh; Chien, Shao-Yi; Chao, Wei-Min; Huang, Yu-Wen; Chen, Liang-Gee
國立臺灣大學 2004-05 Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile Chen, Ching-Yeh; Chien, Shao-Yi; Chao, Wei-Min; Huang, Yu-Wen; Chen, Liang-Gee
臺大學術典藏 2018-09-10T04:47:19Z Hardware architecture for global motion estimation for MPEG-4 advanced simple profile Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN
國立交通大學 2014-12-08T15:09:16Z Hardware Architecture for High-Performance Regular Expression Matching Lee, Tsern-Huei
中華大學 2011 Hardware Architecture of Real-Time Stereoscopic Image Generation from Depth Map 鄭芳炫; Cheng, Fang Hsuan
國立臺灣大學 2007 Hardware Architecture to Realize Multi-layer Image Processing in Real-time Fu, Li-Chen; Lu Chieh-Lun
臺大學術典藏 2018-09-10T06:30:49Z Hardware architecture to realize multi-layer image processing in real-time Fu, Li-Chen; Lu Chieh-Lun; LI-CHEN FU
亞洲大學 2007-12-20 Hardware Context Switching Methodology for Dynamically Partially Reconfigurable Systems Trong-Yen Lee; Che-Cheng Hu; Li-Wen Lai; Chia-Chun Tsai and Rong-Shue Hsiao
國立成功大學 2016-06 Hardware Design and Implementation for Empirical Mode Decomposition Chen, Pei-Yin; Lai, Yen-Chen; Zheng, Ju-Yang
國立臺灣科技大學 2017 Hardware design for statistical network traffic classifiers Lu, C.-N;Lai, Y.-C;Huang, C.-Y;Lin, Y.-D.
國立交通大學 2018-08-21T05:56:54Z Hardware Design for Statistical Network Traffic Classifiers Lu, Chun-Nan; Lai, Yuan-Cheng; Huang, Chun-Ying; Lin, Ying-Dar
國立彰化師範大學 1995 Hardware Design of A Real-Time Petri Net Model for Real-Time Tasks 黃其泮;何正信
國立成功大學 2018-11 Hardware Design of an Energy-Efficient High-Throughput Median Filter Lin;Shih-Hsiang;Chen;Pei-Yin;Lin;Chang-Hsing
國立臺灣科技大學 2010 Hardware design of features extraction using wavelet packet method for intelligent diagnostic system Huang C.-C.; Huang C.-H.; Tsao Y.-M.; Huang S.-C.; Huang H.-L.
國立成功大學 2017-08-1 Hardware Design of Low-Power High-Throughput Sorting Unit Lin;Shih-Hsiang;Chen;Pei-Yin;Lin;Yu-Ning
國立臺灣大學 1997-06 Hardware efficient design of filter banks for video coding Wu, Po-Cheng; Chen, Liang-Gee; Liu, Yuan-Chen; Lai, Yeong-Kang
臺大學術典藏 2018-09-10T06:20:27Z Hardware efficient design of filter banks for video coding Wu, Po-Cheng; Chen, Liang-Gee; Liu, Yuan-Chen; Lai, Yeong-Kang; LIANG-GEE CHEN
國立交通大學 2014-12-08T15:03:36Z Hardware efficient skip mode detection for H.264/AVC Lin, Chia-Chun; Lin, Yu-Kun; Chang, Tian-Sheuan
國立交通大學 2014-12-08T15:27:17Z Hardware efficient transform designs with cyclic formulation and subexpression sharing Chang, TS; Jen, CW
臺大學術典藏 2018-09-10T05:57:28Z Hardware enhanced mining for association rules Liu, W.-C.; Liu, K.-H.; Chen, M.-S.; MING-SYAN CHEN
國立臺灣大學 2010 Hardware Equivalence and Property Verification Jiang, Jie-Hong R.; Villa, Tiziano
臺大學術典藏 2018-09-10T08:19:13Z Hardware Equivalence and Property Verification Jie-Hong R. Jiang;Tiziano Villa; Jie-Hong R. Jiang; Tiziano Villa; JIE-HONG JIANG
臺大學術典藏 2020-06-11T06:11:11Z Hardware Equivalence and Property Verification. Jiang, Jie-Hong Roland;Villa, Tiziano;Crama, Yves;Hammer, Peter L.; Jiang, Jie-Hong Roland; Villa, Tiziano; Crama, Yves; Hammer, Peter L.; JIE-HONG JIANG

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