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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T04:15:05Z	A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme	P. F. Lin; J. B. Kuo; JAMES-B KUO
國立成功大學	2008-09	A 0.8-V 250-MSample/s double-sampled inverse-flip-around sample-and-hold circuit based on switched-opamp architecture	Ou, Hsin-Hung; Liu, Bin-Da; Chang, Soon-Jyh
國立成功大學	2022	A 0.8-μW and 74-dB High-Pass Sigma-Delta Modulator with OPAMP Sharing and Noise-Coupling Techniques for Biomedical Signal Acquisition	Lee, S.-Y.;Lee, H.-Y.;Kung, C.-H.;Su, P.-H.;Chen, J.-Y.
國立成功大學	2022	A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend	Wang, J.-C.;Kuo, T.-H.
國立交通大學	2014-12-08T15:25:24Z	A 0.8V 5.9GHz wide tuning range cmos VCO using inversion-mode bandswitching varactors	Wu, CY; Yu, CY
國立高雄師範大學	2008-12	A 0.8V Folded-Cascode Low Noise Amplifier for Multi-band Applications	Ruey-Lue Wang;Shih-Chih Chen;Cheng-Lin Huang;Chang-Xing Gao;Yi-Shu Lin; 王瑞祿
國立臺灣師範大學	2014-10-30T09:28:41Z	A 0.8V SOP-Based Cascade Multibit Delta-Sigma Modulator for Wideband Applications	Chien-Hung Kuo; Kuan-Yi Lee; Shuo-Chau Chen
國立臺灣師範大學	2014-10-30T09:28:40Z	A 0.8V SOP-Based Wideband Fourth-Order Cascade Delta-Sigma Modulator	Chien-Hung Kuo; Shuo-Chau Cheng
國立交通大學	2017-04-21T06:50:06Z	A 0.8V, 43.5 mu W ECG Signal Acquisition IC with a Referenceless Time-to-Digital Converter	Lin, Shu-Hsuan; Lin, Fu-To; Cheng, Nai-Chen; Liao, Yu-Te
元智大學	2017-06-04	A 0.9-GHz Fully Integrated 45% PAE Class-E Power Amplifier Fabricated Using a 0.18-μm CMOS Process for LoRa Applications	Yu-Ting Tseng; Jeng-Rern Yang

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