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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:08:27Z	A 1-V, 16.9 ppm/℃, 250 nA Switched-Capacitor CMOS Voltage Reference	H. W. Huang; C. Y. Hsieh; K. H. Chen,; S. Y. Kuo; SY-YEN KUO
國立成功大學	2007-06	A 1-V, 6-mA, 3-6 GHz broadband 0.18 mu m CMOS low-noise amplifier for UWB receiver	Chang, C. P.; Yen, C. C.; Chuang, Huey-Ru
國立交通大學	2014-12-08T15:13:37Z	A 1-V, Low-Power CMOS LNA for Ultra-wideband Receivers	Chang, Po Yang; Wu, Hui-I; Jou, Christina F.
國立成功大學	2023-03	A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process	Wang;Chua-Chin;Sangalang;Ralph, Gerard B.;Tseng;I-Ting;Chiu;Yi-Jen;Lin;Yu-Cheng;Jose;Oliver, Lexter July A.
國立中山大學	2000-02	A 1.0 GHz 0.6-µm 8-bit carry lookahead adder using PLA-styled all-N-transistor logic	C.C. Wang;C.J. Huang;K.C. Tsai
國立中山大學	1997-08	A 1.0 GHz 64-bit parallel comparator using two-phase clocking ANT dynamic logic	C.C. Wang;K.C. Tsai
國立中山大學	2001-09	A 1.0 GHz clock generator design with a negative delay using a single-shot locking method	C.C. Wang;Y.L. Tseng;R.S. Kao
臺大學術典藏	2018-09-10T09:16:57Z	A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition	LIANG-GEE CHEN; Chen, L.-G.; Tsai, C.-Y.; Lee, Y.-J.; Chen, C.-T.
國立成功大學	2023	A 1.0�fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process	Wang, C.-C.;Sangalang, R.G.B.;Tseng, I.-T.;Chiu, Y.-J.;Lin, Y.-C.;Jose, O.L.J.A.
國立交通大學	2020-10-05T02:02:22Z	A 1.1-3.1-GHz Tunable Quadruplexer with Compact Size and Bandwidth Control	Chi, Pei-Ling; Chi, Yu-Wen; Yang, Tao

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