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Showing items 92076-92085 of 2351396  (235140 Page(s) Totally)
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Institution Date Title Author
國立暨南國際大學 2010 A 4.9-dB NF 53.5-to 62-GHz MICROMACHINED CMOS WIDEBAND LNA WITH SMALL GROUP-DELAY-VARIATION 陳志成?; Chen, CC
國立暨南國際大學 2010 A 4.9-dB NF 53.5-to 62-GHz MICROMACHINED CMOS WIDEBAND LNA WITH SMALL GROUP-DELAY-VARIATION 林佑昇?; Lin, YS
臺大學術典藏 2018-09-10T04:59:55Z A 4.92-5.845GHz Direct-Conversion CMOS Transceiver for IEEE 802.11a Wireless LAN E. Lin; K. Carter; M. Kappes; Z.M. Shi; L. Lin; S. Wu; S. An; ; T. Nguyen; D. Yuan; Y.C. Wong; V. Fong; B. Yeung; A. Rofougaran; A. Behzad; TSUNG-HSIEN LIN et al.
國立臺灣科技大學 2016 A 4.9GHz low power QVCO using injection locked techniques for wireless wearable applications Lai, W.-C;Jang, S.-L;Su, Su S.-S.
國立交通大學 2019-04-02T06:04:37Z A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking Hung, Chia-Tse; Huang, Yu-Ping; Chen, Wei-Zen
國立交通大學 2014-12-08T15:30:06Z A 40 Gbps Optical Receiver Analog Front-End in 65 nm CMOS Chou, Shun-Tien; Huang, Shih-Hao; Hong, Zheng-Hao; Chen, Wei-Zen
國立交通大學 2014-12-08T15:08:35Z A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18 mu m CMOS Technology Tsai, Chia-Ming
國立交通大學 2014-12-08T15:36:13Z A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist Chiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te
國立交通大學 2015-07-21T11:20:58Z A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist Lien, Nan-Chun; Chu, Li-Wei; Chen, Chien-Hen; Yang, Hao-I.; Tu, Ming-Hsien; Kan, Paul-Sen; Hu, Yong-Jyun; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei
國立交通大學 2014-12-08T15:32:53Z A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia

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