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显示项目 92276-92285 / 2351408 (共235141页)
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| 臺大學術典藏 |
2002-06 |
A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology
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Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang; Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang |
| 國立臺灣大學 |
2002-06 |
A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology
|
Liu, Ren-Chieh; Lee, Chung-Rung; Wang, Huei; Wang, Chorng-Kuang |
| 元智大學 |
2002-08 |
A 5.8Ghz CMOS RF Image-Rejection Receiver Front-end using 90-degree Delayed-Lock Loop
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吳紹懋; Ron-Yi Liu; Sin-Yu Chen |
| 元智大學 |
2003-10 |
A 5.8GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications
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吳紹懋; 劉榮宜; 陳威良 |
| 臺大學術典藏 |
2018-09-10T08:14:45Z |
A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs
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Yang, C.-H.;Yu, T.-H.;Markovi?, D.; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG |
| 國立交通大學 |
2019-09-02T07:45:41Z |
A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems
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Ng, Chee-Kit; Lin, Yu-Chun; Jou, Shyh-Tye |
| 國立交通大學 |
2019-10-05T00:09:47Z |
A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems
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Ng, Chee-Kit; Chiu, Kang-Lun; Lin, Yu-Chun; Jou, Shyh-Jye |
| 國立臺灣大學 |
2008 |
A 50 GHz Divide-by-4 Injection Lock Frequency Divider Using Matching Method
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Chuang, Mei-Chen; Kuo, Jhe-Jia; Wang, Chi-Hsueh; Wang, Huei |
| 國立交通大學 |
2017-04-21T06:55:43Z |
A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting
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Chen, Po-Hung; Wu, Chung-Shiang; Lin, Kai-Chun |
| 臺大學術典藏 |
2009 |
A 50 to 70 GHz power amplifier using 90 nm CMOS technology
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Kuo, J.-L.;Tsai, Z.-M.;Lin, K.-Y.;Wang, H.; Kuo, J.-L.; Tsai, Z.-M.; Lin, K.-Y.; Wang, H.; HUEI WANG; KUN-YOU LIN |
显示项目 92276-92285 / 2351408 (共235141页)
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每页显示[10|25|50]项目
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