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教育部委托研究计画 计画执行:国立台湾大学图书馆
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显示项目 92256-92265 / 2348487 (共234849页) << < 9221 9222 9223 9224 9225 9226 9227 9228 9229 9230 > >> 每页显示[10|25|50]项目
| 國立臺灣大學 |
2004 |
A 5GHz LNA with new compact gain controllable active balun for ISM band applications
|
Rajashekharaiah, Mallesh; Upadhyaya, Parag; Heo, Deukhyoun; Chen, Yi-Jan Emery |
| 國立臺灣科技大學 |
2007 |
A 5GHz low phase noise hartley quadrature CMOS VCO
|
Jang S.-L.; Chen H.-M.; Han J.-C.; Lee C.-F.; Jhuang Y.-D. |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A 5GHz Phase-Locked Loop Using Dynamic Phase-Error Compensation Technique for Fast Settling in 0.18-μm CMOS
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W.-H. Chiu;Y.-H. Huang;T.-H. Lin; W.-H. Chiu; Y.-H. Huang; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T05:50:33Z |
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications
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Lin, C.-P.; Tseng, P.-C.; Chiu, Y.-T.; Lin, S.-S.; Cheng, C.-C.; Fang, H.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 亞洲大學 |
2010-11 |
A 5V/200V SOI Device with a Vertically Linear Graded Drift Region
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楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey |
| 國立臺灣大學 |
2007 |
A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler
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Chen, Hsiao-Chin; Wang, Tao; Lu, Shey-Shi |
| 國立臺灣科技大學 |
2007 |
A 6 GHz low power differential VCO
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Jang, S.-L.;Lee, S.-H.;Chiu, C.-C.;Chuang, Y.-H. |
| 臺大學術典藏 |
2002-05 |
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
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Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei |
| 國立臺灣大學 |
2002-05 |
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
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Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan |
| 國立交通大學 |
2014-12-08T15:25:24Z |
A 6 similar to 10-GHz ultra-WideBand tunable LNA
|
Chen, YC; Kuo, CN |
显示项目 92256-92265 / 2348487 (共234849页) << < 9221 9222 9223 9224 9225 9226 9227 9228 9229 9230 > >> 每页显示[10|25|50]项目
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